Raised Source/Drain Spacers for Parasitic Capacitance Reduction
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Solution Overview
Problem
As integrated circuits are downscaled to 22 nm and smaller, epitaxial raised source/drain (RSD) structures in CMOS devices lead to increased parasitic capacitance between the gate and RSD regions, negatively impacting radio-frequency performance in terms of speed and noise.
Innovation Solution
The method involves forming dielectric or air-gap spacer regions using epitaxial RSD structures grown by selective epitaxial growth, where the RSD regions have a faceted side portion that contacts the gate spacers, reducing fringe capacitance by filling cavity regions with dielectric material or creating air gaps between the gate spacers and RSD regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If epitaxial raised source/drain structures are implemented to reduce source/drain resistance and enable ultra shallow junctions, then manufacturing precision and device performance are improved, but parasitic capacitance between gate and RSD regions increases
Solution Approach 1:
A dielectric spacer is introduced as an intermediary material between the gate electrode and the raised source/drain regions. This spacer physically separates the gate from the RSD regions, reducing the electric field coupling and thereby decreasing parasitic capacitance while maintaining the benefits of elevated RSD structures for shallow junctions
Solution Approach 2:
The solution transitions from a planar gate-RSD configuration to a three-dimensional structure by adding vertical spacing through the dielectric spacer. This dimensional change increases the separation distance between gate and RSD regions, effectively reducing parasitic capacitance without compromising the shallow junction depth achieved by epitaxial growth
2Device complexity
If conventional nonelevated source/drain regions are used for sub-0.25 μm CMOS technology, then device simplicity is maintained, but source/drain resistance cannot be sufficiently reduced while maintaining shallow extension junctions
Solution Approach 1:
The source/drain structure is segmented into multiple components: a buried extension junction region for shallow doping, and an elevated RSD region formed by selective epitaxial growth. This segmentation allows independent optimization of junction depth and resistance characteristics, achieving low RSD resistance with ultra shallow extensions while maintaining manageable device complexity
3Reliability
If heavily doped source/drain regions are used to reduce resistance, then source/drain resistance is reduced, but extension junction depth increases beyond shallow junction requirements
Solution Approach 1:
The extension junctions are formed first with shallow depth and appropriate doping, then the RSD regions are elevated through selective epitaxial growth. This preliminary action sequence allows the extension junctions to be precisely controlled at shallow depths while the subsequent epitaxial growth adds height to reduce resistance, achieving both low resistance and shallow junction depth
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces parasitic capacitance by approximately 80% compared to conventional FETs, enhancing transistor performance by decreasing fringe capacitance and improving RF performance.
Implementation Method 1
epitaxial RSD regions grown by selective epitaxial growth
Data Source
AI summary
A semiconductor structure and method of manufacturing the same are provided. The semiconductor device includes epitaxial raised source/drain (RSD) regions formed on the surface of a semiconductor substrate through selective epitaxial growth. In one embodiment, the faceted side portions of the RSD regions are utilized to form cavity regions which may be filled with a dielectric material to form dielectric spacer regions. Spacers may be formed over the dielectric spacer regions. In another embodiment, the faceted side portions may be selectively grown to form air gap spacer regions in the cavity regions. A conformal spacer layer with interior and exterior surfaces may be formed in the cavity region, creating an air gap spacer defined by the interior surfaces of the conformal spacer layer.