Raised Source-Drain TFT Contacts to Cut Overlap Capacitance
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Solution Overview
Problem
Current embedded semiconductor oxide thin film transistors with a bottom gate and top source-drain contact structure suffer from harmful overlap capacitance due to vertical overlap between the source-to-gate and drain-to-gate regions, leading to transistor delay.
Innovation Solution
The introduction of additional oxide semiconductor or insulator in contact holes before depositing contact material prevents vertical overlap, reducing overlap capacitance and contact resistivity by using a process that includes depositing oxide semiconductor material on the active channel layer, filling contact holes with sacrificial material, and performing chemical-mechanical-planarization to polish contact metal layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a bottom gate and top source-drain contact structure is used, then the transistor can be fabricated with standard processes, but harmful overlap capacitance is introduced due to vertical overlap between source-to-gate and drain-to-gate regions
Solution Approach 1:
The patent applies dimensionality change by transitioning from a planar contact structure to a raised three-dimensional contact structure. The source and drain contacts are elevated above the gate structure, changing the spatial relationship from overlapping in the same plane to separated in the vertical dimension. This resolves the overlap capacitance issue while maintaining fabrication compatibility through sequential deposition and planarization steps.
Solution Approach 2:
The patent employs preliminary action by forming the source and drain contacts before final gate structure completion. The contacts are initially deposited and planarized, then the gate structure is formed around them. This sequence prevents the contacts from extending into the channel region under the gate, eliminating overlap capacitance while using standard fabrication processes.
2Reliability
If source and drain contacts extend into channel regions, then contact area is increased for better electrical connection, but parasitic capacitance increases causing transistor delay
Solution Approach 1:
The patent resolves this contradiction by moving the contacts to a raised dimension above the gate structure. This provides sufficient contact area for reliable electrical connection through the raised contact region and underlying doped regions, while the vertical separation prevents parasitic capacitance formation with the gate, eliminating transistor delay.
Solution Approach 2:
The patent introduces an intermediary approach by using a raised contact structure that acts as a mediator between the need for large contact area and the need to avoid overlap. The raised contact provides extended surface area for reliable electrical connection while its elevated position prevents direct overlap with the gate, resolving the time delay issue.
3Object-affected harmful factors
If additional oxide semiconductor or insulator is added to contact holes, then overlap capacitance is reduced, but manufacturing process complexity increases
Solution Approach 1:
The patent merges multiple functions into the raised contact structure itself. The raised contact serves simultaneously as the electrical contact, the spacing element that prevents overlap, and the structure that defines the contact region boundaries. This integration eliminates the need for separate oxide semiconductor or insulator layers in contact holes, reducing process complexity while maintaining low parasitic capacitance.
Solution Approach 2:
The raised contact structure performs multiple functions: providing electrical connection, preventing overlap capacitance, defining contact boundaries, and serving as a spacer. This multi-functionality replaces what would otherwise require separate materials and process steps, such as additional oxide semiconductor or insulator layers, thereby reducing overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance, enhancing transistor speed and performance by preventing the source-drain contacts from extending into the channel regions.
Implementation Method 1
performing chemical-mechanical-planarization to polish contact metal layers
Data Source
AI summary
A device is disclosed. The device includes a source contact in a source contact trench and a drain contact in a drain contact trench, a channel under the source contact and the drain contact, a first spacing layer on a bottom of the source contact trench and a second spacing layer on a bottom of the drain contact trench. The first spacing layer and the second spacing layer are on the surface of the channel. The device also includes a gate electrode below the channel and a dielectric above the gate electrode and underneath the channel.