Rake Receiver Oscillator Control via Auto Frequency Controller

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Solution Overview

Problem

Current mobile communication systems face performance degradation due to timing offsets in Wideband Code Division Multiple Access (WCDMA) receivers, which are not effectively mitigated by oversampling, increasing complexity and memory usage without fully compensating for timing offsets.

Innovation Solution

A receiver configuration that controls an oscillator based on timing position information to minimize performance degradation, allowing for reduced timing offsets without the need for oversampling, by utilizing an auto frequency controller to adjust the oscillator and move the timing position to maximize signal-to-noise ratio.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If oversampling rate is increased to reduce timing offset, then timing offset compensation improves, but device complexity and memory usage increase

Engineering Contradiction:
Improvetiming offset compensationVSAvoiddevice complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent changes the parameter of oversampling rate from fixed high values (4x, 8x) to a lower value (2x) combined with a可调 frequency offset compensation mechanism. The auto frequency controller dynamically adjusts the frequency offset parameter based on detected timing offsets, achieving precise timing compensation without requiring high oversampling rates, thus reducing device complexity while maintaining measurement precision.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent introduces an auto frequency controller as an intermediary component that detects timing offsets and generates corresponding frequency offset compensation signals. This mediator enables indirect timing offset compensation through frequency domain adjustment rather than direct time-domain oversampling, reducing the need for high oversampling rates and associated complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If oversampling rate is increased to reduce timing offset, then timing offset compensation improves, but memory usage increases

Engineering Contradiction:
Improvetiming offset compensationVSAvoidmemory usage
Core Design Contradiction:
Measurement precisionVSQuantity of substance

Solution Approach 1:

The patent changes the parameter of oversampling rate from fixed high values (4x, 8x) to a lower value (2x) combined with a可调 frequency offset compensation mechanism. The auto frequency controller dynamically adjusts the frequency offset parameter based on detected timing offsets, achieving precise timing compensation without requiring high oversampling rates, thus reducing device complexity while maintaining measurement precision.

Inventive Principle:
Principle #35Parameter changes

3Measurement precision

If 8-times oversampling is performed to reduce timing offset from 1/8 to 1/2 chip, then timing offset reduction improves, but device complexity increases considerably

Engineering Contradiction:
Improvetiming offset reductionVSAvoiddevice complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent changes the parameter of oversampling rate from fixed high values (4x, 8x) to a lower value (2x) combined with a可调 frequency offset compensation mechanism. The auto frequency controller dynamically adjusts the frequency offset parameter based on detected timing offsets, achieving precise timing compensation without requiring high oversampling rates, thus reducing device complexity while maintaining measurement precision.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent introduces an auto frequency controller as an intermediary component that detects timing offsets and generates corresponding frequency offset compensation signals. This mediator enables indirect timing offset compensation through frequency domain adjustment rather than direct time-domain oversampling, reducing the need for high oversampling rates and associated complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Ease of manufacture

If fixed oversampling rate is used, then implementation is simple, but timing offset of 1/(oversampling rate*2) cannot be overcome

Engineering Contradiction:
Improveimplementation simplicityVSAvoidtiming offset compensation capability
Core Design Contradiction:
Ease of manufactureVSMeasurement precision

Solution Approach 1:

The patent transforms the static fixed oversampling rate approach into a dynamic system where the auto frequency controller continuously detects timing offsets and adjusts frequency offset compensation in real-time. This dynamic adaptation enables the system to overcome timing offsets beyond the fixed limit of 1/(oversampling rate*2) while maintaining implementation simplicity through a unified 2x oversampling architecture.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent introduces an auto frequency controller as an intermediary component that detects timing offsets and generates corresponding frequency offset compensation signals. This mediator enables indirect timing offset compensation through frequency domain adjustment rather than direct time-domain oversampling, reducing the need for high oversampling rates and associated complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP3226427B1Rake receiver and receiving method thereof
Publication Date: 2019.06.26 LG ELECTRONICS INC
  • EP3226427B1 patent drawingFigure 1
  • EP3226427B1 patent drawingFigure 2
  • EP3226427B1 patent drawingFigure 3

AI summary

A disclosure of the present specification provides a rake receiver. The rake receiver may comprise: an oscillator; a radio frequency integrated circuit (RFIC) for processing analog signals, which are received after experiencing multipath propagation, according to a sampling clock generated by the oscillator and a carrier frequency clock; a rake processing unit for allocating fingers for each path to signals output from the RFIC, and then performing decoding, wherein the rake processing unit outputs information on a timing position through time tracking, a power metric sampled on-time, and the difference between a power metric at a half chip early-time and a power metric at a half chip late-time; and an auto frequency controller (AFC) for calculating a beta (β) value for adjusting the sampling clock of the oscillator according to the ratio of the difference between the power metric at the half chip early-time and the power metric at the half chip late-time to the power metric sampled on-time.