RAM Control Device Arbiter Circuit Asynchronous Clock Access
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Solution Overview
Problem
Existing RAM control devices face challenges in controlling access to RAM with asynchronously inputted access clocks without increasing device scale and cost, and existing solutions either require additional components like oscillation circuits or have limitations in clock integration.
Innovation Solution
A RAM control device incorporating an arbiter circuit and a one-shot circuit to generate busy signals and a RAM clock, allowing asynchronous access clocks to control RAM access efficiently, minimizing device scale and cost by using a single-port RAM and avoiding the need for complex clock arbitration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a dual-port RAM is used to control access according to two asynchronously inputted access clocks, then access control capability is improved, but chip area and device cost increase
Solution Approach 1:
The patent segments the dual-port RAM functionality into a single-port RAM combined with an arbiter circuit. The arbiter circuit divides the access control into multiple stages: receiving asynchronous access clocks, generating busy signals, and coordinating access timing. This segmentation allows using a smaller single-port RAM while maintaining dual-access capability through temporal division.
Solution Approach 2:
The patent introduces an arbiter circuit as an intermediary between the two asynchronous access clocks and the single-port RAM. This mediator generates busy signals that coordinate access requests, preventing conflicts while enabling both access ports to operate with the same physical RAM resource.
2Area of stationary object
If a single-port RAM is used instead of dual-port RAM, then chip area and cost are reduced, but access control reliability deteriorates due to asynchronous clock conflicts
Solution Approach 1:
The patent implements feedback through busy signals generated by the arbiter circuit. When one access port is actively using the RAM, the arbiter generates a busy signal that feedbacks to the other access port, preventing simultaneous access conflicts. This feedback mechanism ensures reliable access control while using a single-port RAM.
Solution Approach 2:
The arbiter circuit performs preliminary action by generating busy signals in advance before actual RAM access occurs. This preliminary coordination ensures that access conflicts are prevented before they can happen, maintaining reliability without requiring a dual-port RAM.
3Ease of operation
If external access clocks are integrated into internal clock signals, then access coordination is improved, but device scale and cost increase due to additional oscillation circuits
Solution Approach 1:
The patent extracts the clock generation function from the main device by using external access clocks directly. Instead of integrating oscillation circuits to generate internal clocks, the design takes out the clock generation to external sources and only retains the essential arbiter logic for coordination, reducing device scale while maintaining access coordination capability.
4Device complexity
If one control signal is integrated into another control signal, then clock arbitration is simplified, but adaptability deteriorates because the second control signal must remain alive all the time
Solution Approach 1:
The patent applies dynamics by making the arbiter circuit adaptable to different clock signal conditions. The busy signal generation logic dynamically responds to the presence or absence of access clocks, allowing either clock to be inactive or variable in frequency without requiring one clock to continuously dominate. This dynamic behavior maintains simplicity while improving adaptability.
Data Source
AI summary
In a RAM control device, an arbiter circuit is means for generating BUSY1 and BUSY2 of exclusive logic with CLK1 and CLK2 so as to give a right to access RAM3 to a host which has transmitted the first access clock and requesting a one-shot circuit to generate RAMCLK for deciding the timing to access the RAM3. The one-shot circuit is means for generating one pulse of RAMCLK with CLKRQ from the arbiter circuit and transmitting it to the RAM3. This configuration suppresses increase of the device size and cost and enables appropriate control of access to the RAM according to the access clocks of two systems inputted asynchronously.