RAM BIST Interface Serial Data Conversion
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Solution Overview
Problem
Existing BIST techniques for testing random access memory (RAM) devices require high overhead in routing data lines and parallel bit evaluation, which can lead to inefficiencies and increased complexity.
Innovation Solution
A low overhead built-in self test (BIST) technique using a serial-to-parallel data conversion mechanism through a shift register in the memory interface, allowing for serial transfer of test data with a BIST controller, finite state machine, test data generator, address generator, and comparator to manage test operations, reducing routing overhead and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If parallel bit evaluation with comparator is used for testing each bit of output data path, then test coverage is improved, but routing overhead and device complexity increase
Solution Approach 1:
The patent extracts the parallel comparison function from the memory interface and implements it externally using a separate comparator device. The memory device only performs serial data output, while the external comparator handles the parallel evaluation of test results, thereby reducing the memory device's internal complexity and routing overhead while maintaining comprehensive test coverage
Solution Approach 2:
The patent introduces an intermediary external comparator device that mediates between the memory device's serial output and the final test result evaluation. This intermediary handles the complex parallel comparison operations, allowing the memory device to maintain a simpler architecture with reduced routing requirements
2Device complexity
If serial transfer of test data is used instead of parallel, then routing overhead is reduced, but test time increases
Solution Approach 1:
The patent employs periodic clocked operations where the serial-to-parallel conversion and comparison operations are performed in synchronized periodic cycles. This allows the system to process test data efficiently through structured periodic operations, mitigating the time penalty of serial transfer through optimized timing and batch processing
Solution Approach 2:
The patent performs preliminary serial-to-parallel data conversion before the actual comparison operation. By pre-converting the serial data into parallel format in advance, the system prepares the data for rapid parallel comparison, thereby reducing the overall test time despite the initial serial transfer requirement
Data Source
AI summary
Built-In Self Test (BIST) is a test technique wherein semiconductor integrated circuit devices test themselves during their operation lifetime. BIST techniques do not necessarily require additional hardware; they can be implemented using dedicated software routines. Various BIST algorithms and techniques have been proposed for testing random access memory (RAM) devices. The present invention provides an architecture for the memory-test interface that allows the serial transfer of the test background data from the BIST controller to the interface of the memory-under-test using a single bit with serial-to-parallel data conversion using a shift register in the memory interface. The size of the shift register is equal to the word width of the memory-under-test.