RAM Error Correction Using Bit-Index Check Codes
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Solution Overview
Problem
Current Error Checking and Correcting (ECC) technologies in Random Access Memory (RAM) are limited in generality and require changes in polynomial generation when data bit width changes, making them less versatile and more complex.
Innovation Solution
A method and apparatus that set binary index numbers for each data bit, generate first and second check codes through exclusive-or operations based on these indices, and compare them to correct data errors, allowing for error detection and correction without being bound by specific data bit widths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional ECC technology with fixed polynomial generation is used for specific data bit widths, then error correction capability is achieved, but the method lacks generality and requires changes when data bit width changes
Solution Approach 1:
The patent applies universality by designing a check code generation method that works across multiple data bit widths (8, 16, 32, 64, 128 bits) using the same core algorithm. The binary index number approach creates a universal polynomial generation mechanism that adapts to different data widths without requiring separate polynomial sets, making the ECC system multi-functional and broadly applicable.
Solution Approach 2:
The patent utilizes parameter changes by varying the data bit width parameter while maintaining the same check code generation algorithm. The system dynamically adapts to different data widths by changing the index number parameters rather than changing the fundamental polynomial generation method, allowing flexible adaptation to different memory configurations.
2Reliability
If traditional ECC check code generation is used, then error detection and correction is achieved, but the check code scale becomes large
Solution Approach 1:
The patent applies partial action by generating check codes only for the specific data bit width being used, rather than generating check codes for all possible widths. The system performs exactly the necessary XOR operations based on the actual data size, avoiding redundant check code generation and reducing the overall check code scale while maintaining sufficient error correction capability.
3Adaptability or versatility
If data bit width changes in traditional ECC, then different data widths are supported, but polynomial generation must be changed accordingly
Solution Approach 1:
The patent implements universality by creating a single polynomial generation algorithm that serves multiple data bit width requirements. The same check code generation logic works for 8, 16, 32, 64, and 128-bit data widths, eliminating the need to manufacture or implement different polynomial sets for different widths and greatly simplifying the implementation process.
Data Source
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AI summary
Provided are a data error correcting method and device, and computer storage medium, the method comprising: respectively setting an index number for each data bit, and generating a first check code according to the index number; and generating a second check code according to the first check code, comparing the first check code with the second check code to determine an erroneous data bit, and correcting the erroneous data bit. The device comprises: a setting module configured to respectively set the index number for each data bit; a first check code generation module configured to generate the first check code according to the index number; a second check code generation module configured to generate the second check code according to the first check code; and a data processing module configured to compare the first check code with the second check code to determine an erroneous data bit, and correct the erroneous data bit.