On-Chip RAM Buffer Segmentation for Non-Volatile Memory Read Acceleration
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Solution Overview
Problem
Existing non-volatile memory devices, such as serial EEPROM and Flash memory, have lower transfer rates compared to other types of memory, making them less capable as main non-volatile memory devices, and they lack efficient security features for secure data access.
Innovation Solution
Incorporating an on-chip RAM as a buffer memory that operates in conjunction with internal EEPROM/Flash memory, using segment registers to manage address ranges and enhance read operations, and implementing security functions to ensure secure data access and transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is read directly from internal EEPROM/Flash memory, then the memory device maintains simplicity and non-volatile storage, but read speed is slow compared to random-access memory
Solution Approach 1:
The buffer memory is divided into multiple segments that can be independently managed and mapped to different address ranges. This segmentation allows selective buffering of frequently accessed data regions, improving read speed for those regions while maintaining the simplicity of direct EEPROM/Flash access for other regions.
Solution Approach 2:
A buffer memory acts as an intermediary between the master controller and the internal EEPROM/Flash memory. The buffer temporarily stores data that is frequently accessed, allowing fast reads from the buffer while the slower EEPROM/Flash memory maintains the persistent storage function. This intermediary layer resolves the speed contradiction by providing a fast access path for hot data.
2Productivity
If a buffer memory is added to accelerate reads, then read speed improves to be comparable to random-access memory, but the device complexity increases
Solution Approach 1:
The buffer memory and segment register system are integrated into a unified address mapping mechanism. The segment registers work together with the buffer segments to provide automatic address translation, merging the buffering function with the existing address decoding logic. This reduces the perceived complexity by combining multiple functions into a cohesive system.
Solution Approach 2:
The buffer memory system is designed to be universally applicable across different address ranges and data access patterns. The segment registers can be configured to map different virtual address ranges to buffer segments, making the system adaptable to various productivity requirements without requiring separate specialized structures for each case.
3Ease of operation
If segment registers are used to manage address ranges, then address mapping efficiency improves, but the control logic complexity increases
Solution Approach 1:
The segment registers are pre-configured with base addresses, limits, and offsets during system initialization or setup. This preliminary configuration allows the address mapping to proceed automatically during normal operation without requiring complex real-time calculations. The matching logic simply compares the virtual address against the pre-stored segment parameters, significantly reducing control logic complexity during runtime.
Data Source
AI summary
A method of accessing data in a non-volatile memory device is disclosed. The method includes serially receiving a command having an address in a virtual address space. When the address maps to the buffer in memory, the address may be matched to the address to one of a plurality of segments in buffer memory. Data may be moved from internal EEPROM/Flash memory to a segment of the plurality of segments of the buffer memory for an address range in the virtual address space that is likely to be read. A physical address may be generated within the buffer memory based on the address. Data may be fetched in the buffer memory based on the generated address and then a response for the command may be transmitted that includes the fetched data.