RAM/CAM In-Memory AES Fabric for Parallel Encryption Throughput
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Solution Overview
Problem
Existing AES encryption/decryption methods face computational inefficiencies in software implementations and hardware accelerators often trade off between area/power efficiency and parallelism, with emerging memory technologies prolonging write latencies.
Innovation Solution
A programmable in-memory computing (IMC) fabric using RAM/CAM arrays for parallel processing, combining operations like SubByte/MixColumns for encryption and InvSubBytes/AddRoundKey/InvMixColumns for decryption, supported by a RISC-V-based controller for flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If software-based AES implementation is used, then flexibility and ease of operation are maintained, but computational efficiency and throughput are low
Solution Approach 1:
The patent replaces traditional software-based computational mechanisms with in-memory computing mechanisms. Specifically, it uses content-addressable memory (CAM) arrays to perform AES encryption/decryption operations directly within the memory fabric, substituting sequential software processing with parallel hardware-based memory operations. This substitution enables throughput improvement while reducing the computational burden on external processors.
2Productivity
If hardware accelerators (ASICs or FPGAs) are used for AES, then throughput is improved, but area consumption and power consumption increase
Solution Approach 1:
The patent creates a universal in-memory computing fabric that can perform multiple cryptographic operations (AES encryption, AES decryption, and potentially other algorithms) using the same hardware infrastructure. The CAM arrays and lookup table fabric modules are designed to be reconfigurable and multi-functional, allowing a single hardware structure to serve multiple purposes, thereby reducing overall area consumption compared to dedicated ASICs for each operation.
Solution Approach 2:
The patent uses lookup tables stored in memory to represent complex cryptographic transformation functions. Instead of implementing intricate logic circuits for each AES operation, the system copies pre-computed transformation data into memory structures (CAM arrays and lookup tables), allowing the hardware to perform operations by accessing these copied data structures rather than executing complex computational logic, thus reducing area requirements.
3Quantity of substance
If emerging memory technologies (PCMs, RRAMs, STT-MRAMs, FeFET-RAMs) are used for in-memory computing, then density and static power consumption are improved, but write latency increases
Solution Approach 1:
The patent pre-computes and stores cryptographic transformation data (lookup tables for S-box operations, MixColumns matrices, etc.) in the memory fabric before encryption/decryption operations are needed. By performing these computations in advance and storing the results in CAM arrays and lookup tables, the system eliminates the need for real-time computation during actual cryptographic operations, thereby mitigating the impact of longer write latencies associated with emerging memory technologies.
Data Source
AI summary
A secure system configured to perform operations on data can include a plurality of N look-up-table fabric modules each operatively coupled to a respective column of M rows of data included in an input state matrix having N columns and M rows and a processor circuit operatively coupled to the plurality of N look-up-table fabric modules, the processor circuit configured to provide unencrypted data to the plurality of N look-up-table fabric modules for encryption and configured to provide encrypted data to the plurality of N look-up-table fabric modules for decryption.