RAM Clock Gating for BIST Area Reduction
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Solution Overview
Problem
Existing Random Access Memory (RAM) designs face challenges in minimizing area overhead due to the inclusion of Built-In Self-Test (BIST) hardware controllers, which can be significant in small RAMs, impacting testability and efficiency.
Innovation Solution
The implementation of a RAM architecture with an array of storage elements arranged in rows and columns, where each row has a common gated-clock input and respective data inputs, utilizing clock gating circuitry that generates gated-clock signals based on a memory address, test mode signal, and scan enable signal, allowing for efficient test mode operations and reduced area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a Built-In Self-Test (BIST) hardware controller is included in small RAM designs, then testability is improved, but area overhead increases significantly
Solution Approach 1:
The patent extracts the BIST controller from the RAM core and implements it as a separate, dedicated test mode controller. This separation allows the BIST functionality to be added only when needed (during testing) without permanently increasing the area of the operational RAM structure. The controller is integrated into the existing RAM architecture but remains dormant during normal operation.
Solution Approach 2:
The patent makes the existing RAM control logic multi-functional by enabling it to operate in both normal mode and test mode. The same control signals and logic structures are reused for both operational and testing purposes, eliminating the need for separate dedicated test hardware and reducing overall area overhead.
2Reliability
If RAM memory matrix is replaced with standard flip-flops and digital control logic, then test coverage is improved, but area penalty increases severely
Solution Approach 1:
Instead of replacing the RAM matrix with flip-flops to achieve testability, the patent inverts the approach by keeping the RAM matrix intact and adding test capabilities through a dedicated controller that operates in test mode. This maintains the area efficiency of the RAM structure while achieving comprehensive test coverage through inverted control logic.
Solution Approach 2:
The patent creates a test mode copy of the control logic that mirrors the normal operational logic. This copied control path is specifically designed to enable thorough testing while sharing the same physical hardware resources, thereby achieving high test coverage without the area penalty of completely replacing the RAM structure with flip-flops.
3Area of moving object
If D type latches with common gated-clock input are used in each row, then area is reduced, but clock distribution complexity increases
Solution Approach 1:
The patent merges the clock gating functionality into a single common gated-clock input for each row of D type latches. Instead of providing individual clock controls to each latch, the same clock signal is distributed to all latches in a row, reducing the number of clock distribution lines and simplifying the overall clocking architecture while maintaining area efficiency.
Data Source
AI summary
A random access memory (RAM) includes an array of arranged in rows and columns. The rows of the storage elements correspond to respective memory locations of the RAM. The storage elements of a row have a common gated-clock input and respective data inputs, and each row of the array of storage elements includes a plurality of D type latches. In operation, an address input of the RAM receives a memory address identifying a memory location in the RAM. Clock gating circuitry of the RAM, generates respective gated-clock signals for the rows of the array of storage elements based on the memory address received at the address input. Memory operation are performed using storage elements of the array based on the gated-clock signals.