RAM Clock Gating for BIST Area Reduction
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Solution Overview
Problem
Existing Random Access Memory (RAM) designs face challenges in minimizing area overhead due to the inclusion of Built-In Self-Test (BIST) hardware controllers, which can be cumbersome for small RAMs, especially in achieving high Automotive quality standards for fault coverage and complexity management.
Innovation Solution
The implementation of a RAM architecture that uses an array of D-type latches with clock gating circuitry, generating gated-clock signals based on memory addresses and test mode signals, allowing for efficient test mode operations and reduced area impact by integrating clock gating cells and test mode control logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Built-In Self-Test hardware controller is included in RAM design, then fault coverage and quality are improved, but area overhead increases significantly
Solution Approach 1:
The patent extracts the BIST controller functionality and separates it from the main RAM array. The BIST controller is implemented as a separate entity that can be instantiated only when needed for testing, rather than being permanently integrated into the RAM structure. This allows the RAM to achieve high fault coverage when testing is required while minimizing area overhead during normal operation.
Solution Approach 2:
The patent implements dynamic configuration where the BIST controller is activated only during test modes and remains inactive during normal data operations. The test mode enable signal dynamically controls the BIST controller's operation, allowing the system to adapt between testing and operational states, thereby reducing average area utilization while maintaining comprehensive fault coverage capability.
2Area of stationary object
If RAM memory size is reduced, then device area is minimized, but area overhead from BIST controller becomes more significant
Solution Approach 1:
For small RAM implementations, the patent extracts the BIST controller as a separate, optional component rather than integrating it into the compact RAM array. This extraction allows the RAM core to maintain minimal area while the BIST functionality can be added only when quality verification is needed, preventing the controller from consuming valuable area in small devices.
Solution Approach 2:
The patent changes the parameter of BIST controller instantiation based on RAM size and testing requirements. For small RAMs, the BIST controller is implemented as a separate module that can be selectively activated, rather than being permanently integrated. This parameter change allows the system to maintain compact size while still achieving high quality through optional testing capability.
3Reliability
If flip-flops are used to replace RAM matrix for testing, then test coverage is improved, but area penalty becomes severe
Solution Approach 1:
The patent extracts the testing functionality from a complete flip-flop replacement approach. Instead of replacing the entire RAM matrix with flip-flops, the patent maintains the efficient RAM array structure and extracts only the necessary test coverage capabilities through a separate BIST controller that works with the existing RAM cells. This selective extraction achieves test coverage without the severe area penalty of full replacement.
Solution Approach 2:
The patent implements multi-functionality where the RAM array serves both its primary data storage function and its test function simultaneously. The BIST controller enables the same RAM cells to be used for both normal operations and testing, eliminating the need for separate test structures. This universality achieves comprehensive test coverage without duplicating the entire memory matrix with flip-flops.
Data Source
AI summary
A random access memory (RAM) includes an array of arranged in rows and columns. The rows of the storage elements correspond to respective memory locations of the RAM. The storage elements of a row have a common gated-clock input and respective data inputs, and each row of the array of storage elements includes a plurality of D type latches. In operation, an address input of the RAM receives a memory address identifying a memory location in the RAM. Clock gating circuitry of the RAM, generates respective gated-clock signals for the rows of the array of storage elements based on the memory address received at the address input. Memory operation are performed using storage elements of the array based on the gated-clock signals.