RAM-Based Decimation Filter for PLDs Without Overclocking
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Solution Overview
Problem
Programmable logic devices (PLDs) with digital signal processing (DSP) blocks face challenges in performing decimation filtering without overclocking, especially at high input data rates, as existing solutions require running portions of the DSP block at several times the input data rate.
Innovation Solution
The use of available random access memory (RAM) instead of shift registers in PLDs to store data and coefficients, allowing all components of the filter to operate at the same rate as the input data samples, with address generation sequences modified based on symmetry structures to mimic shift register behavior.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If shift registers are used in DSP blocks to implement decimation filters, then the filter can process data sequentially, but portions of the DSP block must run at several times the input data rate (overclocking)
Solution Approach 1:
The patent replaces the mechanical shift register structure with a memory-based system using random access memory (RAM) blocks. Instead of sequentially shifting data through registers, the invention uses RAM to store data samples and employs address generation logic to access stored samples, eliminating the need for overclocked operation of DSP components.
Solution Approach 2:
The patent introduces address generation logic as an intermediary component that manages data flow between the input interface and the DSP blocks. This address generation unit creates incremental pointers to access RAM contents, effectively mediating the data sequence requirement without requiring the DSP blocks to operate at multiple times the input rate.
2Ease of operation
If RAM is used instead of shift registers, then all DSP components can operate at the input data rate without overclocking, but additional address generation logic is required
Solution Approach 1:
The patent makes the address generation logic adaptable to different filter configurations by implementing support for multiple symmetry structures (no symmetry, odd symmetry, and even symmetry). The same address generation unit can be reconfigured through programming to handle different decimation factors and symmetry requirements, reducing the need for dedicated hardware for each configuration.
3Duration of action of moving object
If discrete memory blocks are used for each multiplier, then data and coefficients can be stored for many clock cycles, but the amount of RAM required increases
Solution Approach 1:
The patent merges the functionality of multiple discrete memory blocks into shared RAM resources. Instead of providing separate memory blocks for each multiplier, the invention uses a pool of RAM blocks that can be dynamically allocated and shared among multiple multipliers through time-multiplexed access, reducing the total RAM capacity required while maintaining the ability to store data for many clock cycles.
Data Source
AI summary
A programmable integrated circuit device such as a programmable logic device can be configured as a finite impulse response (FIR) filter capable of operating in decimation mode. The device includes at least one user-configurable random access memory block, and that user-configurable random access memory is configured as coefficient memories and data sample memories. The memories are large enough to hold up to all of the coefficients of the filter and a plurality of data samples at one time. Because the data samples and coefficients need not be shifted through the filter at the programmable logic device clock rate, overclocking of the filter is not necessary. The filter can run at a clock rate which is the same as the input data rate, while taking advantage of the available random access memory to mimic a shift register.