RAM ECC Interleaving for Multi-Bit Error Protection

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Solution Overview

Problem

As process technologies shrink, traditional error-correction codes (ECCs) become insufficient in protecting data against multi-bit error events that corrupt larger numbers of adjacent bit cells in RAM, and increasing the multiplexing (MUX) factor leads to poor area efficiency and timing constraints, especially in smaller RAM blocks.

Innovation Solution

Divide data into sections, apply ECC to each section, and interleave them to form codewords that are written to memory, allowing traditional single-bit ECC techniques to correct errors across multiple sections, thereby protecting against multi-bit errors without the need for slower multi-error correction codes or high MUX factors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional single-bit ECC codes are used, then error correction capability is sufficient for small error events, but protection against multi-bit errors caused by scaled-down process technologies is insufficient

Engineering Contradiction:

Improvedata protection capabilityVSAvoidmulti-bit error susceptibility

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The data is divided into multiple sections, with each section protected by its own ECC code. This segmentation allows the system to handle multi-bit errors by treating them as multiple single-bit errors across different sections, maintaining protection capability without requiring complex multi-bit ECC codes.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent transforms the error protection approach from a single-dimensional multi-bit ECC code to a multi-dimensional structure where multiple single-bit ECC codes protect different sections of data. This dimensional transformation enables protection against multi-bit errors while using simpler single-bit correction codes.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Reliability

If multi-error correction codes are used to protect against multi-bit errors, then data protection capability improves, but processing speed decreases significantly

Engineering Contradiction:

Improvemulti-bit error protectionVSAvoiderror correction speed

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

By segmenting data into multiple sections and applying single-bit ECC codes to each section independently, the system achieves multi-bit error protection through parallel processing of simpler codes, maintaining high speed while improving reliability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent changes the error correction parameter from correcting multiple bits in a single code to correcting single bits in multiple separate codes. This parameter transformation enables the use of faster single-bit ECC algorithms while achieving equivalent or superior multi-bit error protection.

Inventive Principle:

Principle #35Parameter changes

3Reliability

If the MUX factor is increased to protect against multi-bit errors, then error protection capability improves, but area efficiency and timing performance deteriorate

Engineering Contradiction:

Improvemulti-bit error protectionVSAvoidRAM block area efficiency

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent segments the protection mechanism across multiple ECC codes rather than using a single high-MUX interleaved structure. This segmentation allows for more flexible and compact RAM block design, improving area efficiency while maintaining error protection capability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Instead of increasing the MUX factor to achieve multi-bit error protection, the patent inverts the approach by using multiple lower-MUX ECC codes working in parallel. This inversion achieves the same protection goal with better area efficiency and timing performance.

Inventive Principle:

Principle #13The other way round (Inversion)

4Reliability

If the MUX factor is increased to protect against multi-bit errors, then error protection capability improves, but timing constraints worsen

Engineering Contradiction:

Improvemulti-bit error protectionVSAvoidtiming performance

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

Segmenting the error protection into multiple independent single-bit ECC codes allows each code to be processed quickly without the complex interleaving operations required by high-MUX factors, reducing timing loss while maintaining protection capability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent inverts the conventional approach of using high MUX factors for multi-bit protection and instead uses multiple low-MUX ECC codes. This inversion achieves multi-bit error protection with significantly better timing performance.

Inventive Principle:

Principle #13The other way round (Inversion)

Data Source

PatentUS20130080859A1Method for providing data protection for data stored within a memory element and integrated circuit device therefor

Publication Date: 2013.03.28 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method for providing data protection for data stored within a Random Access Memory element. The method comprises receiving data to be written to memory, dividing the received data into a plurality of data sections, applying error correction codes to the data sections to form codeword sections, interleaving the codeword sections to form an interleaved data codeword, and writing within a single clock cycle the interleaved data codeword to memory.