Multi-Core MCU RAM ECC Self-Diagnosis Logic

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Solution Overview

Problem

Conventional technologies cannot effectively diagnose errors in the RAM error detection logic of powertrain controllers, specifically the ECC module, and distinguish between actual and false operations, leading to potential control malfunctions in vehicles.

Innovation Solution

A method and apparatus for self-diagnosis of RAM error detection logic in a powertrain controller using a multi-core microcontroller unit, where each core idles and tests the ECC module corresponding to another core's RAM, performing three types of error detection tests to verify the error detection function without affecting powertrain control.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the ECC module is enabled to detect memory errors, then memory error detection capability is improved, but the ability to diagnose errors in the ECC module itself deteriorates

Engineering Contradiction:
Improvememory error detection capabilityVSAvoidECC module self-diagnosis capability
Core Design Contradiction:
ReliabilityVSDifficulty of detecting and measuring

Solution Approach 1:

The patent uses another core's ECC module as an intermediary to test the first core's ECC module. This mediator approach allows the ECC module to be tested by an independent entity, enabling self-diagnosis of the ECC module without compromising its primary error detection function. The cross-core testing arrangement provides an objective perspective for diagnosing ECC module errors.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

Instead of having each core test its own ECC module (self-testing), the patent inverts the approach by having one core's ECC module test another core's ECC module. This inversion enables the testing mechanism to operate independently from the module being tested, allowing for proper diagnosis of ECC module functionality without the module testing itself.

Inventive Principle:
Principle #13The other way round (Inversion)

2Difficulty of detecting and measuring

If a multi-core system is used to perform cross-core ECC tests, then ECC module self-diagnosis capability is improved, but system complexity and test coordination requirements increase

Engineering Contradiction:
ImproveECC module self-diagnosis capabilityVSAvoidtest coordination complexity
Core Design Contradiction:
Difficulty of detecting and measuringVSDevice complexity

Solution Approach 1:

The patent makes each core's ECC module universal by enabling it to test not only its own associated RAM but also RAM modules associated with other cores. This multi-functionality allows any core to serve as a tester for any other core's ECC module, reducing the need for dedicated testing hardware and simplifying the overall system architecture while maintaining comprehensive diagnostic capability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent segments the testing process into discrete, manageable tasks that can be executed by individual cores. Each core can independently idle its associated RAM and ECC module, then perform tests on another core's ECC module. This segmentation allows for systematic test coordination without requiring complex inter-core communication protocols, as each core operates semi-independently in the testing sequence.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11347582B2Method and apparatus for self-diagnosis of ram error detection logic of powertrain controller
Publication Date: 2022.05.31 HYUNDAI AUTOEVER
  • US11347582B2 patent drawing
  • US11347582B2 patent drawing
  • US11347582B2 patent drawing

AI summary

A method for the self-diagnosis of RAM error detection logic of a powertrain controller includes: idling, by a first core, an operation of a second core; testing an error correction code (ECC) module corresponding to a RAM operating by the second core; idling, by the second core, an operation of a core of a plurality of un tested cores; and testing an ECC module corresponding to a RAM operating by the core of the plurality of untested cores.