RAM Flash Memory Cell Low Voltage Operation
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Solution Overview
Problem
Conventional memory devices face challenges in operating at low voltages while maintaining high density and low energy consumption, particularly in advanced systems that require tight metal pitch and low voltage compatibility, with existing flash memory cells requiring high voltages and having slow data access times, and volatile memory cells being power-hungry and physically large.
Innovation Solution
The development of RAM Flash memory cells, which are modified flash memory cells configured to operate at low voltages (≤6V) with reduced dielectric layer thickness, allowing for low voltage program and erase operations and compatibility with advanced logic flows at small metal pitch rules, and offering flexible retention-hold approaches to prolong data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If conventional flash memory cells are used, then data retention is improved (>10 years), but operational voltage increases (>10V) and data access time increases (slow)
Solution Approach 1:
The patent modifies the flash memory cell structure by changing the thickness parameter of the tunnel oxide layer and control gate dielectric layer. By reducing the tunnel oxide thickness to enable low-voltage Fowler-Nordheim tunneling while adjusting control gate dielectric thickness to maintain data retention, the invention achieves both low operational voltage and long data retention simultaneously.
2Duration of action of stationary object
If conventional flash memory cells are used, then data retention is improved (>10 years), but data access speed worsens (slow access time)
Solution Approach 1:
The patent optimizes the thickness parameters of dielectric layers to enable faster charge/discharge cycles. The reduced tunnel oxide thickness allows quicker electron tunneling for program/erase operations, while the control gate dielectric structure maintains charge storage capability for data retention, thus improving access speed without sacrificing retention.
3Speed
If volatile memory cells (SRAM/DRAM) are used, then data access speed is improved (fast), but device area increases (physically large)
Solution Approach 1:
The patent uses a 1T (one-transistor) flash memory cell structure that segments the memory function into distinct components: the transistor for charge control and the floating gate for data storage. This segmentation allows the cell to achieve small area comparable to flash memory while providing fast access speeds through direct transistor control, unlike multi-transistor SRAM cells.
4Speed
If volatile memory cells (SRAM/DRAM) are used, then data access speed is improved (fast), but power consumption increases (power hungry)
Solution Approach 1:
The patent employs low-voltage operation parameters (reduced tunnel oxide thickness enabling operation at lower voltages) combined with Fowler-Nordheim tunneling mechanism that requires less continuous power compared to refresh operations in DRAM or complex decode circuits in SRAM. The one-transistor structure reduces static power consumption while maintaining fast access through direct charge injection and removal.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
RAM Flash cells provide improved data retention, reduced power consumption, and lower operational voltages compared to conventional flash memory cells, enabling integration into microcontrollers and CPUs with reduced size, cost, and increased performance, along with lower data refresh frequencies and bus latency.
Implementation Method 1
configured to operate at low voltages (≤6V) with reduced dielectric layer thickness, allowing for low voltage program and erase operations
Data Source
AI summary
A memory cell having a structure of a modified flash memory cell, but configured to operate in a low voltage domain (e.g., using voltages of ≤6V amplitude for program and/or erase operations) is provided. The disclosed memory cells may be formed with dielectric layers having reduced thickness(es) as compared with conventional flash memory cells, which allows for such low voltage operation. The disclosed memory cells may be compatible with advanced, high density, low energy data computational applications. The disclosed memory cells may replace or reduce the need for RAM (e.g., SRAM or DRAM) in a conventional device, e.g., microcontroller or computer, and are thus referred to “RAM Flash” memory cells. Data retention of RAM Flash memory cells may be increased (e.g., to days, months, or years) by (a) applying a static holding voltage at selected nodes of the cell, and/or (b) periodically refreshing data stored in RAM Flash.