Dynamic RAM Frequency Control via Cache Hit Ratio

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Solution Overview

Problem

Existing memory systems face challenges in reducing power consumption of random access memory (RAM) while minimizing performance degradation.

Innovation Solution

The system dynamically adjusts the operating frequency of RAM based on the cache hit ratio, determining the size of data accessed and setting the frequency accordingly to optimize performance and power usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If the operating frequency of random access memory is reduced to decrease power consumption, then power consumption is reduced, but memory access speed deteriorates

Engineering Contradiction:
Improvepower consumption of random access memoryVSAvoidmemory access speed
Core Design Contradiction:
Use of energy by moving objectVSSpeed

Solution Approach 1:

The patent implements dynamic frequency adjustment of the random access memory based on the cache hit ratio. When the cache hit ratio is high, the RAM frequency is reduced to save power; when the cache hit ratio is low, the RAM frequency is increased to maintain performance. This dynamic adaptation resolves the contradiction by making the frequency adjustable rather than fixed.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the operating frequency parameter of the random access memory based on system conditions (cache hit ratio). By monitoring the cache hit ratio and adjusting the RAM frequency accordingly, the system optimizes the balance between power consumption and access speed, resolving the technical contradiction through parameter adaptation.

Inventive Principle:
Principle #35Parameter changes

2Speed

If the operating frequency of random access memory is increased to improve memory access speed, then memory access speed is improved, but power consumption increases

Engineering Contradiction:
Improvememory access speedVSAvoidpower consumption of random access memory
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The system dynamically adjusts the RAM operating frequency based on real-time cache hit ratio monitoring. When high performance is needed (low cache hit ratio), frequency increases; when power saving is prioritized (high cache hit ratio), frequency decreases. This dynamic control resolves the contradiction between speed and power consumption.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The operating frequency parameter of the random access memory is changed based on system conditions. By adapting the frequency parameter to the cache hit ratio, the system achieves optimal performance while minimizing power consumption, resolving the speed-power contradiction.

Inventive Principle:
Principle #35Parameter changes

3Use of energy by moving object

If dynamic frequency adjustment is implemented based on cache hit ratio, then power consumption is optimized, but system complexity increases

Engineering Contradiction:
Improvepower consumption optimizationVSAvoidsystem complexity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The patent implements a feedback mechanism where the cache hit ratio is monitored and used to adjust the RAM frequency. This closed-loop control optimizes power consumption by continuously adapting to system conditions, resolving the contradiction between optimization and complexity through intelligent feedback-based control.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS12332788B2System setting including operating frequency of random access memory based on cache hit ratio and operating method thereof
Publication Date: 2025.06.17 SK HYNIX INC
  • US12332788B2 patent drawing
  • US12332788B2 patent drawing
  • US12332788B2 patent drawing

AI summary

Embodiments of the present disclosure relate to a system and an operating method of the system. Based on some embodiments of the disclosed technology, the system may include a random access memory structured to include memory cells to store data, a cache memory configured to cache at least part of the data, and a processor in communication with the random access memory and the cache memory to access at least part of the data from the random access memory or cache memory. The system may determine a cache hit ratio for the cache memory, and may set an operating frequency of the random access memory based on the cache hit ratio.