Multi-Bank RAM Signal Buffering via Global and Local Inverters
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Solution Overview
Problem
In multi-bank RAM structures, the increased resistance-capacitance time constant of global connectors beyond the 32 nm technology node leads to poor signal slew rates, necessitating the use of buffers that increase area consumption, peak power consumption, and latency.
Innovation Solution
Incorporating inverters into both global and local connectors to provide even signal buffering, ensuring that signals are buffered by an even number of inverters, thereby improving slew rates and reducing power consumption while minimizing area expansion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If buffers are incorporated into global connectors to improve slew rates, then signal propagation performance is improved, but area consumption increases
Solution Approach 1:
The patent divides the signal buffering function into two segments: global buffers located at global connector nodes and local buffers located at local connectors. This segmentation allows each buffer to serve a smaller, more localized group of memory banks, reducing the total number of buffers needed while maintaining signal integrity across the entire memory array.
Solution Approach 2:
The patent implements local buffering at local connectors that are specific to individual memory banks or groups of banks. This local quality approach ensures that each memory bank receives appropriately buffered signals tailored to its specific location and requirements, rather than using a uniform global buffering approach for all banks.
2Speed
If buffers are incorporated into global connectors to improve slew rates, then signal propagation performance is improved, but peak power consumption increases
Solution Approach 1:
By segmenting the buffering function into global and local components, the patent reduces the simultaneous switching activity of large global buffers. Local buffers switch independently and can be staggered in time, reducing peak power consumption while still providing the necessary slew rate improvement for signal integrity.
3Speed
If buffers are incorporated into global connectors to improve slew rates, then signal propagation performance is improved, but latency increases
Solution Approach 1:
The segmented buffering approach allows signals to be buffered locally at the connector level rather than requiring long global buffer chains. This reduces the total buffering path length and number of buffer stages, thereby reducing cumulative latency while still providing adequate slew rate control for signal integrity.
4Area of stationary object
If global connectors are made longer to reach more memory banks, then coverage is improved, but RC time constant increases
Solution Approach 1:
The patent segments the long global connector into multiple shorter segments by inserting global buffers at intermediate nodes. This segmentation breaks the continuous long RC time constant into smaller, manageable segments, each with lower RC values, thereby maintaining signal integrity across the extended coverage area.
Solution Approach 2:
Global buffers positioned at intermediate nodes of the global connector act as intermediaries that actively drive signals across long distances. These intermediary buffers compensate for the increasing RC time constant by providing signal regeneration and driving strength, enabling the global connector to reach more memory banks while maintaining signal integrity.
Data Source
AI summary
Disclosed are embodiments of a multi-bank random access memory (RAM) structure that provides signal buffering at both the global and local connector level for improved performance. Specifically, inverters are incorporated into the global connector(s), which traverse groups of memory banks and which transmit signals (e.g., address signals, control signals, and/or data signals) from a memory controller, and also into alternating groups of local connectors, which connect nodes on the global connector(s) to corresponding groups of memory banks, such that any of the signals that are received by the memory banks from the memory controller via the global and local connectors are buffered by an even number of inverters and are thereby true signals. Signal buffering at both the global and local connector level results in relatively fast slews, short propagation delays, and low peak power consumption with minimal, if any, increase in area consumption.