Flexible RAM Loader Using Parallel Register Sections for Test Time Reduction
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Solution Overview
Problem
Current RAM loading methods for microcontroller devices, which rely on serial data loading, are time-consuming due to the need to load kilobits of data, leading to prolonged test operations and manufacturing bottlenecks.
Innovation Solution
A flexible RAM loading device and method that utilizes a shift register and test register with multiple data sections and selection bits, enabling parallel data loading from multiple pins, and includes a MUX to toggle between functional RAM control signals and data from the test register, allowing for efficient data transfer to the RAM.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If serial data loading is used to load kilobits of data into RAM, then the device structure remains simple, but the test operation time becomes excessively long
Solution Approach 1:
The loading device is segmented into multiple functional blocks including a shift register divided into first and second data sections, a test register, and multiple MUXes. Each section can be independently configured to handle different data loading modes (serial or parallel), allowing the system to achieve high-speed parallel loading when resources permit while maintaining simplicity when pins are limited.
Solution Approach 2:
The loading device dynamically adapts its operating mode based on the number of available pins. Through control signals and selection bits, the device can switch between serial loading mode (when pins are scarce) and parallel loading mode (when pins are abundant), optimizing test speed without requiring a fixed complex structure.
2Productivity
If parallel data loading from multiple pins is implemented, then data loading speed increases significantly, but the device structure and control logic become more complex
Solution Approach 1:
The shift register and test register are designed as multi-functional components that can operate in both serial and parallel modes. The same hardware blocks serve dual purposes: the shift register can load data serially from a single pin or in parallel from multiple pins, and the test register similarly adapts its loading mode based on available resources, reducing the need for separate dedicated circuits for each mode.
Solution Approach 2:
Multiple MUXes (multiplexers) are introduced as intermediary components that manage the complexity of parallel data loading. These MUXes selectively route data from different sources (external pins or internal shift register sections) to the appropriate destinations, enabling flexible parallel loading while keeping the control logic centralized and manageable through selection bits.
3Adaptability or versatility
If the loading device adapts to different pin configurations, then versatility improves, but control logic complexity increases
Solution Approach 1:
The device adapts to different pin configurations by changing its operational parameters through selection bits and control signals. The number of active parallel data sections, the width of parallel loading, and the mode of operation (serial vs. parallel) are all adjustable parameters that can be configured based on the available pins, allowing the same hardware to optimize performance for different device types without requiring multiple dedicated circuits.
Data Source
AI summary
A flexible RAM loader including a shift register that includes a first data section coupled with a serial data input, and a second data section selectively coupled with a first parallel data input. The shift register is configured to load data serially from the serial data input to the first data section and the second data section when the second data section is uncoupled from the first parallel data input, and, when the second data section is coupled with the first parallel data input, configured to load data in parallel from the serial data input into the first data section and from the first parallel data input into the second data section. The flexible RAM loader also including a test register comprising a selection bit to couple the second data section with the first parallel data input.