RAM Memory Cell Array Blocks with Standard Cell Peripheral Logic
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Solution Overview
Problem
Modern System on Chip (SoC) designs require large memory subsystems with conflicting demands on area, access time, and power consumption, leading to memory bandwidth and routing congestion issues in existing RAM solutions.
Innovation Solution
A method for designing integrated circuits with random-access memory that divides memory into smaller, tightly packed portions, generating memory cell array blocks without peripheral logic, and synthesizing them with standard cell-compatible peripheral logic to optimize area and routing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If large RAM blocks are used to minimize area overhead, then area efficiency is improved, but routing congestion and bandwidth issues worsen
Solution Approach 1:
The patent divides the large RAM block into multiple smaller memory portions (e.g., four 8Kx16 bits memory portions instead of one 32Kx16 bits memory portion). Each memory portion is implemented as a separate memory cell array block with its own peripheral logic, enabling independent placement and routing. This segmentation reduces routing congestion by distributing connections across multiple smaller blocks rather than routing through a single large block, while maintaining area efficiency through compact memory cell array implementations.
2Adaptability or versatility
If standard cell based memories are used for flexibility, then adaptability is improved, but area penalty worsens
Solution Approach 1:
The patent segments the memory system into multiple memory portions that can be independently configured and placed. Each memory portion uses memory cell array blocks with peripheral logic synthesized from standard cells, combining the area efficiency of custom RAM structures with the flexibility of standard cell-based design. The segmentation allows each block to be optimized independently while using standard cell infrastructure for placement and routing.
Solution Approach 2:
The patent enables parameter tuning of the memory system by allowing different configurations of memory portions (e.g., number of ports, access widths, depths) to be synthesized from standard cells. The peripheral logic for each memory portion can be customized through standard cell synthesis, providing flexibility in memory parameters while maintaining area efficiency through optimized memory cell array block layouts.
3Device complexity
If single or dual port RAM blocks are used, then device complexity is reduced, but memory bandwidth issues worsen
Solution Approach 1:
The patent implements multiple memory portions, each with its own peripheral logic and access ports. This segmentation enables parallel access to different memory portions simultaneously, increasing overall memory bandwidth. Each memory portion can be independently accessed through separate ports, eliminating the bottleneck of single or dual port limitations in conventional RAM blocks while maintaining manageable complexity through modular design.
Data Source
AI summary
A computer-implemented method for implementing integrated circuit with at least one RAM includes: defining memory portions of the RAM and obtaining memory portions; for each memory portion, generating a memory cell array block corresponding to the sizes of the memory portions, instances of the memory cell array blocks are inferred into a description of the integrated circuit in a hardware description language; for each block, generating timing and physical models; synthesizing description of circuit in the language, including peripheral logic for the blocks, to schematic representation of circuit elements; placing circuit elements, including blocks and peripheral logic, on circuit and routing wires between circuit elements taking into account the timing and physical models of blocks. An integrated circuit has memory portions of RAM, each having memory cell array block without, or partly without, peripheral logic; logic for each block implemented as standard cells, blocks and the logic distributed over circuit.