In-Cache RAM Multiplexer Architecture for Word-Level Multiplication

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Solution Overview

Problem

Current in-cache computing architectures for random access memories (RAM) face inefficiencies in performing multiplications due to low bitcell density, data corruption risks, and high latency, particularly in deep neural networks, where 90% of operations require word-level multiplications, while previous solutions only support bitwise operations.

Innovation Solution

The proposed RAM architecture includes local memory groups with local bitlines, a bitline multiplexer, and embedded shift circuits, enabling associativity-agnostic operations and reducing data misalignment, along with a subarray controller for optimized multiplication operations, allowing for efficient word-level multiplications and reduced latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If bitwise operations are used in current in-cache computing architectures, then circuit complexity is reduced, but multiplication performance deteriorates due to inability to perform word-level multiplications

Engineering Contradiction:

Improvecircuit complexityVSAvoidmultiplication performance

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

The bitline computing architecture is enhanced to perform multiple functions: it can execute both bitwise operations (AND, OR, XOR) and word-level multiplications using the same hardware infrastructure. The local bitline multiplexer and shift circuits enable the system to switch between different operation modes, making the architecture universal and eliminating the need for separate multiplication circuits.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The architecture changes the operational parameters by introducing shift circuitry that can dynamically adjust the number of shifts (0-31 bits) based on multiplication requirements. This parameter change enables the system to perform word-level multiplications by shifting and adding partial products, transforming the capability from simple bitwise operations to full arithmetic multiplication.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If data placement is constrained to avoid way misalignment, then data corruption is prevented, but multiplication latency increases due to limited data access flexibility

Engineering Contradiction:

Improvedata integrityVSAvoidmultiplication latency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

Local bitline multiplexers are introduced as intermediary components between the memory array and the computation logic. These multiplexers act as mediators that can selectively connect different bitlines to the computation unit, enabling flexible data access patterns without causing way misalignment or data corruption. The intermediary allows the system to access data from multiple ways simultaneously while maintaining data integrity.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Adaptability or versatility

If local bitline multiplexer is added to each local memory group, then associativity-agnostic operations are enabled, but device complexity increases

Engineering Contradiction:

Improveassociativity-agnostic capabilityVSAvoidlocal group periphery complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The memory array is segmented into multiple local memory groups, each with its own local bitline multiplexer. This segmentation allows each group to operate independently and perform associativity-agnostic operations without affecting other groups. The segmentation distributes the complexity across multiple small units rather than requiring a single complex global multiplexer, making the overall system more manageable and scalable.

Inventive Principle:

Principle #1Segmentation

4Productivity

If embedded shift circuits are implemented, then word-level multiplication is enabled, but area overhead increases

Engineering Contradiction:

Improvemultiplication capabilityVSAvoidmemory array area

Core Design Contradiction:

ProductivityVSArea of stationary object

Solution Approach 1:

The shift circuits are merged with the existing bitline computing infrastructure rather than being implemented as separate dedicated multiplication units. The shift functionality is integrated into the local group periphery, sharing resources with the bitline multiplexer and computation logic. This merging approach enables word-level multiplication while minimizing area overhead by reusing existing circuit elements.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS11211115B2Associativity-agnostic in-cache computing memory architecture optimized for multiplication

Publication Date: 2021.12.28 ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)

AI summary

A random access memory array including a plurality of local memory group ways, each local memory group way including, a plurality of local memory groups, each local memory group including, a memory column including a plurality of memory cells, a pair of local bitlines operatively connected to the plurality of memory cells, and a local group periphery including a local bitline multiplexer operatively connected with the pairs of local bitlines of the corresponding local memory group; and a pair of global read bitlines operatively connected to outputs of the plurality of local group peripheries, a global read bitline multiplexer operatively connected to outputs of the plurality of pairs of the global read bitlines from the local memory group ways, and a bitline operational block operatively connected an output of the global read bitline multiplexer.