Output Buffer Initialization for High-Speed Synchronous RAM
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Solution Overview
Problem
Existing output buffer initialization techniques in high-speed synchronous SRAM and RLDRAM applications often result in undesired power up sequences and leakage due to incorrect ordering of power supply voltages, leading to unstable operation states.
Innovation Solution
The implementation of adaptive power up systems with pre-initialized circuitry at the DQ pre-output stage of level-shifters, which maintain high-z states regardless of the ramping order of power supplies, ensuring proper operation during disorderly power up sequences by using configurations such as DQ pull-up and pull-down level-shift circuits and output driver circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If output buffer initialization is implemented to prevent leakage during power up, then power up reliability is improved, but device complexity increases due to additional initialization circuitry
Solution Approach 1:
The patent applies preliminary action by pre-initializing the output buffer to a high-impedance state before the power up sequence completes. The initialization circuitry is activated early during power up to prevent leakage currents before they can occur, rather than responding to leakage after it happens. This is achieved through detection circuits that monitor power up status and trigger initialization proactively.
Solution Approach 2:
The patent uses intermediary elements including detection circuits that monitor power supply voltage levels and control circuits that mediate between the power up sequence and the output buffer initialization. These intermediaries detect the power up state and coordinate the initialization timing, preventing direct conflicts between power supply sequencing and buffer state requirements.
2Adaptability or versatility
If adaptive power up detection is implemented to handle random power up sequences, then adaptability is improved, but device complexity increases due to additional detection and control circuitry
Solution Approach 1:
The patent implements self-service through automatic power up sequence detection and adaptive response. The detection circuits automatically monitor which power supply voltage reaches its operational level first (VDD or VDDQ), and the control logic autonomously adjusts the initialization sequence accordingly. No external intervention or manual configuration is needed - the system detects and adapts to the actual power up sequence occurring in real-time.
Solution Approach 2:
The patent applies parameter changes by dynamically adjusting the initialization timing and sequence based on the detected power up sequence. When VDDQ powers up before VDD, the system changes the initialization parameters to delay certain buffer activations until VDD is ready, preventing leakage while maintaining operational readiness. The detection circuits monitor voltage parameters and trigger appropriate initialization sequences.
3Device complexity
If output buffer initialization is delayed until after power up sequence completion, then device complexity is reduced, but leakage occurs during disorderly power up sequences
Solution Approach 1:
The patent applies preliminary anti-action by implementing initialization circuitry that proactively prevents leakage currents before they can occur during disorderly power up sequences. The detection circuits identify when VDDQ powers up before VDD and trigger early initialization of the output buffer to high-impedance state, counteracting the potential leakage effect before it manifests. This preliminary protective action eliminates the need to wait for the complete power up sequence.
Data Source
AI summary
Systems and methods are disclosed involving adaptive power up features for high-speed synchronous RAM. In one exemplary implementation, there is provided a semiconductor device including a memory cell, power circuitry, and an output buffer with level shifting circuitry. Moreover, the device may include power circuitry comprised of a first power up circuit and a second power up circuit and/or level shifting circuitry comprised of a pull up level shift circuit and a pull down level shift circuit. Other implementations and specific circuit configurations are also disclosed.