Abnormality Detection Circuit for Built-in RAM Relief Signal Monitoring
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Solution Overview
Problem
The increasing complexity and capacity of built-in RAMs in LSI devices lead to higher failure rates, particularly in the memory cell relief circuit, making it difficult to isolate the cause of data abnormalities, which in turn increases man-hours and time for failure analysis.
Innovation Solution
A semiconductor device with an abnormality detection circuit that monitors temporal changes in the relief signal output from the memory cell relief circuit, facilitating the detection of faults in the memory cell relief circuit and improving failure analysis efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the capacity and complexity of built-in RAMs are increased, then the storage capability is improved, but the failure rate in the memory cell relief circuit increases
Solution Approach 1:
The abnormality detection circuit performs preliminary monitoring of the relief signal to detect potential failures before they cause data abnormalities. By continuously comparing the relief signal with expected values and detecting temporal changes, the system identifies faults in the memory cell relief circuit proactively, preventing them from affecting RAM operation.
Solution Approach 2:
The abnormality detection circuit acts as an intermediary between the memory cell relief circuit and the rest of the RAM system. It monitors the relief signal output from the relief decoder circuit and generates abnormality detection signals that indicate the health status of the relief circuit, thereby mediating the reliability issue without affecting the core storage function.
2Quantity of substance
If the memory cell relief circuit complexity increases to handle larger RAM capacity, then the storage capability is improved, but the difficulty of isolating failure causes increases
Solution Approach 1:
The abnormality detection circuit provides feedback about the relief signal status to the system. By continuously monitoring the relief signal and generating abnormality detection signals that indicate whether the relief circuit is functioning normally, the system gains visibility into the relief circuit's operational state, making it easier to identify and isolate failures.
Solution Approach 2:
The patent replaces manual failure analysis and mechanical troubleshooting with an automated electronic detection system. The abnormality detection circuit uses electronic signal comparison and temporal change detection to automatically identify relief circuit failures, substituting the manual process of isolating failures with an automated electronic measurement approach.
3Device complexity
If manual failure analysis is performed without automated detection, then device complexity is reduced, but the time and effort required for failure analysis increases
Solution Approach 1:
The abnormality detection circuit enables the system to self-diagnose relief circuit failures. By automatically monitoring the relief signal and generating abnormality detection signals, the system performs its own failure detection without requiring external manual analysis, thereby reducing the time and effort needed for failure analysis while maintaining relatively simple circuit architecture.
Data Source
AI summary
A semiconductor device includes a plurality of built-in memories, and each of the built-in memories includes a plurality of memory cells. Each built-in memory includes a selector circuit that connects a selected memory cell among the memory cells to an outside, a memory cell relief circuit that, when a fault has occurred in one of the memory cells, transmits, to the selector circuit, a relief signal configured to connect a normal memory cell to the outside without connecting the one of the memory cells in which the fault has occurred, to the outside, and switches selection in the selector circuit, and an abnormality detection circuit that performs abnormality detection for the memory cell relief circuit, based on a temporal change in the relief signal output from the memory cell relief circuit.