RAM Routing Logic for Dynamic Error Correction
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Solution Overview
Problem
Current system-on-chip (SoC) designs for safety applications face complexity and cost due to the need for multiple architectures to support varying Safety Integrity Levels (SIL), with Random Access Memory (RAM) being a significant contributor to potential failures, and existing error detection and correction methods either reduce system availability or are costly.
Innovation Solution
A memory sub-system with at least two RAM elements, error detection or correction logic, and RAM routing logic that dynamically identifies faulty RAM content and selects a correct or corrected value, using error-detecting and error-correcting codes to provide redundant memory storage and high data availability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant RAM elements are implemented to improve safety and availability, then system reliability is improved, but device complexity and cost increase
Solution Approach 1:
The patent implements redundancy by copying data into multiple RAM elements (first RAM element and second RAM element) that are separately accessible. This allows the system to maintain high availability by having backup copies of critical data, while avoiding the need for complex triple-voting architectures by using a simpler dual-copy model with selective accessibility.
Solution Approach 2:
The patent segments the RAM storage into distinct first and second RAM elements with separate accessibility paths. This segmentation allows independent access to each element, enabling the system to detect and correct failures in one element without affecting the other, thereby improving reliability while maintaining manageable complexity.
2Reliability
If triple voting architecture is used to detect and correct errors, then error detection capability is improved, but cost and resource requirements increase
Solution Approach 1:
Instead of implementing expensive triple-voting architecture, the patent uses a simpler copying approach where data is replicated in two separate RAM elements. This dual-copy model provides sufficient error detection and correction capabilities for many applications while significantly reducing the quantity of memory resources and overall system cost.
Solution Approach 2:
The patent applies partial redundancy by implementing only the minimum necessary duplication (two copies instead of three) to achieve adequate error detection and correction. This partial action approach provides sufficient protection against single failures without the excessive resources required by triple-voting systems.
3Adaptability or versatility
If multiple SoC architectures are designed to support different SIL levels, then adaptability to safety requirements is improved, but development complexity and cost increase
Solution Approach 1:
The patent implements a dynamic configuration mechanism where the accessibility of first and second RAM elements can be selectively enabled or disabled based on the required Safety Integrity Level. This allows a single SoC architecture to adapt to different SIL requirements (e.g., SIL 2 or SIL 3) without requiring multiple separate architectures, thereby improving adaptability while reducing development complexity.
Solution Approach 2:
The patent creates a universal RAM architecture that can serve multiple safety levels through configurable accessibility. The same hardware structure with selectively accessible RAM elements can support different SIL levels by adjusting which elements are active, eliminating the need for multiple specialized architectures and reducing overall development complexity.
Data Source
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AI summary
A system comprises at least two random access memory (RAM) elements arranged to store data redundantly. The system further comprises RA M routing logic comprising comparison logic operably coupled to the at least two RAM elements and arranged to compare redundant data read from the at least two RAM elements, and check and validation logic, independent of the RAM routing logic, operably coupled to the at least two RAM elements and arranged to additionally detect an error in the redundant data read from th e at least two RAM elements and provide an error indication signal to the RAM routing logic in re sponse thereto. The RAM routing logic further comprises selection logic arranged to dynamically select redundant data from one of the at least two RAM elements based on the comparison of t he redundant data and the error indication signal.