RAM Segmentation for Multi-Core Switch Buffer Utilization
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Solution Overview
Problem
Ultra-wide band switch chips face challenges in achieving high-frequency multi-read and multi-write capabilities due to limited memory structure, leading to reduced buffer utilization and increased area costs.
Innovation Solution
A data read/write method and device that divide storage regions into unoccupied areas in RAM, allowing each core to acquire and perform read/write operations independently, ensuring one-read one-write per storage region, thereby enabling multiple cores to operate simultaneously without conflicts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a multi-read and multi-write buffer is implemented in traditional memory structure, then the switch capacity is improved, but the frequency is reduced or the area cost increases
Solution Approach 1:
The buffer is divided into multiple storage regions, with each region supporting one-read one-write operations simultaneously. This segmentation allows multiple cores to perform read/write operations in parallel across different regions, achieving multi-read multi-write functionality while maintaining high frequency operation in each region.
2Productivity
If a multi-read and multi-write buffer is implemented in traditional memory structure, then the switch capacity is improved, but the area cost increases
Solution Approach 1:
The buffer is divided into multiple storage regions, with each region supporting one-read one-write operations simultaneously. This segmentation allows multiple cores to perform read/write operations in parallel across different regions, achieving multi-read multi-write functionality while maintaining high frequency operation in each region.
Solution Approach 2:
Each storage region is designed to be universally accessible by multiple cores, with each region supporting both read and write operations. This multi-functionality allows the same memory structure to serve multiple purposes and support multiple cores without requiring separate dedicated memory for each core, thereby reducing overall area cost.
3Device complexity
If traditional memory structure is used for buffer, then the implementation is simple, but the utilization rate of memory is low
Solution Approach 1:
The buffer is divided into multiple storage regions, with each region supporting one-read one-write operations simultaneously. This segmentation allows multiple cores to perform read/write operations in parallel across different regions, achieving multi-read multi-write functionality while maintaining high frequency operation in each region.
Solution Approach 2:
The memory structure transitions from a single unified buffer to multiple segmented storage regions, changing the organizational parameter of the memory. This parameter change enables better utilization by allowing simultaneous access from multiple cores without requiring complex arbitration mechanisms, thus maintaining implementation simplicity while improving utilization rate.
Data Source
AI summary
Disclosed are a data read/write method and apparatus, and an exchange chip and a storage medium. The method comprises: when the current clock cycle arrives, a kernel acquiring a read/write instruction that needs to be executed in the current clock cycle; the kernel acquiring a target storage area associated with the read/write instruction, wherein the target storage area is an unoccupied storage area in at least two storage areas in a random access memory (RAM); and the kernel performing, according to the read/write instruction, data reading and writing on the target storage area in the current clock cycle.