Interleaved RAM Snapshotting for Emulation Trace Buffer Overflow
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current hardware emulation systems face challenges in efficiently tracing memory changes due to the large amount of data generated, which exceeds the capacity of trace buffers, leading to incomplete data capture and unrecoverable memory changes, especially as SoC designs become more complex.
Innovation Solution
A Random Access Memory (RAM) design with interleaved memory cells and a copying mechanism allows for snapshotting the primary memory contents within one clock cycle, enabling efficient data capture and download without interrupting the memory operation, using dual bit cells and separate memory planes to act as independent structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If traditional trace buffer methods are used to capture memory changes, then the trace system can record memory states, but the large amount of data generated exceeds trace buffer capacity, leading to incomplete data capture
Solution Approach 1:
The memory is divided into two separate planes: a primary memory plane that continues normal operation and a snapshot memory plane that captures state changes. This segmentation allows the tracing function to be separated from the main memory operation, enabling complete data capture without overwhelming the trace buffer.
Solution Approach 2:
Instead of directly tracing all memory changes, the invention creates copies of memory state changes in the snapshot memory plane. These copies represent the essential information needed for debugging while consuming minimal trace buffer resources, thus preventing data loss.
2Loss of information
If memory operation is interrupted to download trace data, then complete memory contents can be captured, but the emulator operation is disrupted
Solution Approach 1:
The snapshot memory plane continuously captures and stores memory state changes in the background during normal operation. By the time debugging or analysis is needed, the complete memory state information has already been preliminarily captured and is ready for immediate download without interrupting emulator operation.
Solution Approach 2:
The memory system operates continuously with both the primary plane handling normal operations and the snapshot plane simultaneously capturing state changes. This dual-plane continuous operation ensures that neither debugging data collection nor emulator productivity is compromised.
3Speed
If separate memory planes are used for snapshotting, then memory contents can be captured instantly, but the memory structure becomes more complex
Solution Approach 1:
The snapshot memory plane is merged with the primary memory plane at the physical level, sharing the same memory cell structure and addressing mechanism. This merging allows instant snapshot capture through simple plane selection rather than physical copying, achieving high speed while minimizing structural complexity.
Solution Approach 2:
The dual-plane memory structure serves multiple functions: the primary plane handles normal memory operations while the snapshot plane captures state changes. The same memory infrastructure is used for both debugging and normal operation, making the system multi-functional without proportionally increasing complexity.
Data Source
AI summary
A Random Access Memory (RAM) and method of using the same are disclosed. The RAM includes a plurality of memory cells arranged in columns and in rows with each memory cell coupled to at least one word line and at least one bit line. The RAM includes a plurality of switches with at least one of the switches coupled between two of the memory cells to allow data to be copied from one of the two memory cells to the other of the two memory cells. In another aspect, the two memory cells can be considered a dual bit cell that contains a copying mechanism. There are two interleaved memory planes, assembled from bit cells that contain two bits of information. One bit is the primary bit that corresponds to the normal RAM bit. The second bit is able to receive a copy and hold the primary value. When the copying mechanism is over, the two memory planes may act as two completely independent structures.