RAM Read/Write Speed Testing with Buffer Memory Weighting

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Solution Overview

Problem

Current methods for testing read/write speed of random access memory do not accurately account for the impact of CPU buffer memories, leading to incomplete evaluation of mobile phone performance.

Innovation Solution

A method and apparatus that calculate a weighted average of test speeds from both random access memory and associated buffer memories to determine the actual read/write speed, considering the impact of buffer memories on the overall performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If only random access memory is tested without buffer memory, then test simplicity is maintained, but measurement precision deteriorates because the actual read/write speed cannot be accurately reflected

Engineering Contradiction:
Improveread/write speed measurement accuracyVSAvoidtest system complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent segments the memory testing process into distinct phases: buffer memory testing, random access memory testing, and composite testing. By dividing the testing into separate stages with different configurations, the system achieves comprehensive measurement without requiring a completely complex test architecture. The buffer memory and random access memory are tested independently first, then together to derive the actual performance metrics.

Inventive Principle:
Principle #1Segmentation

2Measurement precision

If buffer memory impact is included in testing, then measurement precision improves, but test complexity increases due to multiple memory components

Engineering Contradiction:
Improveperformance evaluation accuracyVSAvoidtest apparatus complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent employs dynamic testing configurations that can be adjusted between different memory component combinations. The test system dynamically switches between testing buffer memory alone, random access memory alone, and both together, allowing flexible adaptation to different testing scenarios. This dynamic approach enables comprehensive measurement while maintaining operational simplicity through programmable control.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10643736B2Method, apparatus and electronic device for read/write speed testing
Publication Date: 2020.05.05 ZHUHAI JUNTIAN ELECTRONICS TECH
  • US10643736B2 patent drawing
  • US10643736B2 patent drawing
  • US10643736B2 patent drawing

AI summary

The present invention provides a method for read/write speed testing, comprising: obtaining a test speed of reading data from or writing data to each of a plurality of memories, the plurality of memories including a random access memory and at least one buffer memory associated with the random access memory; and determining an actual speed of reading data from or writing data to the random access memory according to the test speed of reading data from or writing data to the each memory. Embodiments of the present invention further disclose an apparatus for read/write speed testing and electronic device. With the embodiments of the present invention, the read/write speed of the random access memory can be tested more accurately.