Hybrid RAM-TCAM Caching for Network Packet Classification
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Solution Overview
Problem
High-speed network devices face limitations in efficiently storing and looking up classification rules due to the high power consumption and large chip area requirements of ternary content-addressable memory (TCAM), which can lead to bandwidth bottlenecks when handling a large number of rules, especially in integrated circuit chips.
Innovation Solution
Implementing a hybrid system that uses a combination of RAM for caching frequently used rule entries and TCAM for less frequently accessed rules, where decision logic extracts classification keys, applies masks to unmasked bits, and computes hashes to facilitate efficient matching and caching, thereby reducing the reliance on TCAM bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If TCAM is used to store all classification rules, then high-speed packet classification is achieved, but power consumption and chip area increase significantly
Solution Approach 1:
The patent divides the classification rules into two segments: frequently accessed rules are stored in RAM while less frequently accessed rules remain in TCAM. This segmentation allows the system to maintain high-speed classification for common patterns while reducing overall power consumption by limiting TCAM usage to only when necessary.
Solution Approach 2:
The system performs preliminary classification using RAM for frequently accessed rules before resorting to TCAM. By pre-processing packets with the more energy-efficient RAM storage, the system reduces the number of times power-hungry TCAM operations are required.
2Speed
If TCAM is used to store all classification rules, then high-speed packet classification is achieved, but chip area requirements increase
Solution Approach 1:
The patent segments the rule storage between RAM and TCAM based on access frequency. Frequently accessed rules occupy smaller RAM space, while less frequently accessed rules occupy TCAM space, thereby reducing the total chip area required compared to storing all rules in TCAM.
Solution Approach 2:
The system creates a copy of frequently accessed rules in RAM, which is a more area-efficient storage medium for these specific rules. This copying strategy allows the system to maintain fast classification performance while reducing the area occupied by the larger, slower TCAM structure.
3Use of energy by stationary object
If all rules are cached in RAM, then power consumption is reduced, but lookup efficiency decreases for less frequently accessed rules
Solution Approach 1:
The patent applies local quality by optimizing for different access patterns: RAM provides fast, low-power access for frequently accessed rules, while TCAM provides comprehensive but power-intensive access for less frequently accessed rules. Each storage medium is used where it provides the most appropriate performance characteristics.
Solution Approach 2:
The system dynamically selects between RAM and TCAM based on whether the classification pattern exists in the frequently accessed subset. This dynamic approach ensures that the system uses the most efficient storage medium for each specific lookup operation.
4Use of energy by stationary object
If a hybrid RAM-TCAM system is used, then power consumption and chip area are optimized, but system complexity increases
Solution Approach 1:
The system performs preliminary classification attempts in RAM before accessing TCAM. This preliminary action simplifies the overall system architecture by providing a clear hierarchical lookup process, where the simpler RAM check is performed first, and only on failure does the system proceed to the more complex TCAM operation.
Data Source
AI summary
Communication apparatus includes a TCAM, which stores a corpus of rules, including respective sets of unmasked and masked bits. The rules conform to respective rule patterns, each defining a different, respective sequence of masked and unmasked bits to which one or more of the rules conform. A RAM caches rule entries corresponding to rules belonging to one or more of the rule patterns that have been selected for caching. Decision logic extracts respective classification keys from data packets, each key including a string of bits extracted from selected fields in a given data packet, and classifies the data packets by first matching the respective classification keys to the cached rule entries in the RAM and, when no match is found in the RAM, by matching the respective classification keys to the rules in the TCAM.


