Ramp ADC Bit Sequencing for Compact Image Sensor Readout
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Solution Overview
Problem
In laminated-type imaging apparatuses, the miniaturization of pixels leads to challenges in downsizing the analog-digital (AD) conversion circuit, resulting in time differences when reading signals from multiple pixels, which can cause distorted imaging or prolonged image acquisition times, especially when capturing moving objects.
Innovation Solution
A conversion apparatus with a comparison unit that compares input signals with a ramp voltage to generate a digital signal of a predetermined bit number, utilizing a storage unit to hold code values repeatedly, allowing for the combination of low-order and high-order bits to produce a digital signal, with the option of using Gray codes and shared bits, and differing ramp signal cycles for high and low signal intensity levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the AD conversion circuit is shared by multiple pixels to downsize the circuit, then the circuit size is reduced, but the time difference between reading signals from multiple pixels increases causing distorted imaging
Solution Approach 1:
The patent divides the pixel array into multiple banks, with each bank having its own dedicated AD conversion circuit. This segmentation allows simultaneous conversion of multiple pixels without time differences, resolving the distortion issue while maintaining compact circuit design through the laminated structure.
Solution Approach 2:
The patent transitions from a planar layout to a three-dimensional laminated structure where pixel circuits are formed on one substrate and AD conversion circuits are formed on another substrate bonded to the first. This dimensional change enables reduced circuit area and improved integration without increasing the footprint.
2Device complexity
If more pixels are handled by one AD conversion circuit to reduce the number of circuits, then the circuit complexity is reduced, but the image acquisition time increases
Solution Approach 1:
The patent segments the imaging system into multiple banks, each with its own AD conversion circuit, enabling parallel processing of pixel signals. This increases image acquisition speed while keeping the total number of circuits manageable through the laminated architecture.
Solution Approach 2:
The patent combines multiple pixel circuits and AD conversion circuits across different substrates in a laminated structure, achieving high integration and parallel processing capability while maintaining compact form factor.
3Measurement precision
If pixels are miniaturized to increase the number of pixels, then the imaging resolution is improved, but the AD conversion circuit becomes difficult to downsize
Solution Approach 1:
The patent moves the AD conversion circuits to a separate substrate in a laminated configuration, allowing pixel miniaturization on the first substrate without being constrained by the physical size requirements of the AD conversion circuits, thus enabling high resolution with compact overall device size.
Solution Approach 2:
The patent segments the system into pixel circuits on one substrate and AD conversion circuits on another, allowing independent optimization of pixel size for resolution while the AD conversion circuits are downsized through the laminated structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the downsizing of the circuit configuration for digital signal generation, reducing the size of the AD conversion circuit and improving imaging speed and accuracy, especially when capturing moving objects, while minimizing distortion and power consumption.
Implementation Method 1
a comparison unit that compares an input voltage of an input signal and a ramp voltage of a ramp signal that varies with time
Implementation Method 2
a storage unit that holds a code value when a comparison result from the comparison unit is inverted, the holding of the code value by the storage unit being repeated a plurality of times, to generate a digital signal having a predetermined bit number
Implementation Method 3
a ramp voltage of a ramp signal that varies with time
Data Source
AI summary
The present technology relates to a conversion apparatus, an imaging apparatus, an electronic apparatus, and a conversion method that are capable of reducing the scale of a circuit.The conversion apparatus includes: a comparison unit that compares an input voltage of an input signal and a ramp voltage of a ramp signal that varies with time; and a storage unit that holds a code value when a comparison result from the comparison unit is inverted, the holding of the code value by the storage unit being repeated a plurality of times, to generate a digital signal having a predetermined bit number. The predetermined bit number is divided into high-order bits and low-order bits, the low-order bits are acquired earlier than the high-order bits, and the acquired low-order bits and the high-order bits are combined with each other, to generate the digital signal having the predetermined bit number. The present technology can be applied to a portion of an image sensor, in which AD conversion is performed.