Ramp ADC Bit-Splitting for Compact Image Sensor Readout
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Solution Overview
Problem
In laminated-type imaging apparatuses, miniaturizing pixels while maintaining image quality and speed is challenging due to the difficulty in downsizing analog-digital (AD) conversion circuits, which are shared among multiple pixels, leading to time differences in signal reading and potential image distortion.
Innovation Solution
A conversion apparatus with a comparison unit that compares input signals with a ramp voltage to generate a digital signal of a predetermined bit number, utilizing a storage unit to hold code values repeatedly, allowing for the combination of low-order and high-order bits to produce a digital signal, with the option of using Gray codes and shared bits, and differing ramp signal cycles for high and low signal intensity levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If multiple pixels share one AD conversion circuit, then the circuit size is reduced, but time differences between read pixels increase causing image distortion
Solution Approach 1:
The patent divides the AD conversion process into multiple independent conversion circuits, with each circuit handling a specific group of pixels. This segmentation allows simultaneous conversion of multiple pixels without time differences, resolving the contradiction between circuit size reduction and image quality maintenance.
Solution Approach 2:
The patent transitions from a single shared AD conversion circuit to a two-dimensional array of multiple AD conversion circuits, where the number of circuits corresponds to the number of pixels. This dimensional change enables parallel processing of multiple pixels while maintaining compact circuit integration.
2Volume of moving object
If pixels are miniaturized, then the imaging apparatus size is reduced, but the circuit mounted on the chip becomes difficult to downsize
Solution Approach 1:
The patent merges the pixel array and AD conversion circuits into a unified laminated structure where photodiodes and transistors are integrated on the same chip. This merging eliminates the need for separate support substrates and enables simultaneous miniaturization of both pixels and circuits.
Solution Approach 2:
The patent employs a three-dimensional laminated structure with multiple layers (first substrate with photodiodes, second substrate with transistors, third substrate with ADCs) to achieve high integration density. This vertical dimensionality allows compact circuit configurations that accompany pixel miniaturization.
3Volume of moving object
If one AD conversion circuit handles many pixels, then the circuit size is reduced, but the reading time increases
Solution Approach 1:
The patent segments the pixel-to-ADC mapping such that multiple ADCs collectively handle all pixels, with each ADC processing a subset of pixels simultaneously. This segmentation reduces the pixel load per ADC and enables parallel signal conversion, thereby reducing total reading time while maintaining compact circuit size.
Solution Approach 2:
The patent implements continuous parallel operation of multiple AD conversion circuits, where all ADCs operate simultaneously to convert signals from their respective pixel groups. This continuous parallel processing eliminates idle time and reduces the overall signal reading time compared to sequential processing by a single ADC.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the downsizing of circuit configurations related to digital signal generation, reducing the size of AD conversion circuits and minimizing image distortion, especially when imaging moving objects, while maintaining high-speed processing and low power consumption.
Implementation Method 1
a comparison unit that compares an input voltage of an input signal and a ramp voltage of a ramp signal that varies with time
Implementation Method 2
a storage unit that holds a code value when a comparison result from the comparison unit is inverted, the holding of the code value by the storage unit being repeated a plurality of times
Data Source
AI summary
The present technology relates to a conversion apparatus, an imaging apparatus, an electronic apparatus, and a conversion method that are capable of reducing the scale of a circuit.The conversion apparatus includes: a comparison unit that compares an input voltage of an input signal and a ramp voltage of a ramp signal that varies with time; and a storage unit that holds a code value when a comparison result from the comparison unit is inverted, the holding of the code value by the storage unit being repeated a plurality of times, to generate a digital signal having a predetermined bit number. The predetermined bit number is divided into high-order bits and low-order bits, the low-order bits are acquired earlier than the high-order bits, and the acquired low-order bits and the high-order bits are combined with each other, to generate the digital signal having the predetermined bit number. The present technology can be applied to a portion of an image sensor, in which AD conversion is performed.