Ramp ADC Latch Architecture for Higher Image Sensor Resolution
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Solution Overview
Problem
Existing analog-to-digital converter (ADC) circuits in image sensors lack the capability to improve resolution efficiently without increasing power consumption or generation time.
Innovation Solution
Incorporation of an additional latch circuit and multiple latch circuits within the ADC circuit, utilizing a ramp generator, clock generator, and comparators to generate additional binary signals and latch signals based on system clock signals, allowing for enhanced resolution with maintained frequency and reduced time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the resolution of the ADC circuit is improved by increasing the number of bits, then the measurement precision is improved, but the generation time and power consumption increase
Solution Approach 1:
The ADC circuit is segmented into multiple independent latch circuits (first to N-th latch circuits) that operate in parallel. Each latch circuit processes a portion of the conversion simultaneously, dividing the overall conversion time into concurrent operations rather than sequential steps, thereby maintaining high resolution while reducing total generation time.
Solution Approach 2:
The ramp generator continuously generates ramp signals in advance, and the latch circuits are pre-configured with clock signals ready to capture comparison results immediately when needed. This preliminary preparation eliminates waiting time during the conversion process, allowing the ADC to deliver high-resolution results without increasing generation time.
2Measurement precision
If the resolution of the ADC circuit is improved by increasing the number of bits, then the measurement precision is improved, but the power consumption increases
Solution Approach 1:
The power consumption is segmented and distributed across multiple independent latch circuits that operate in parallel. Each latch circuit consumes minimal power individually, and their concurrent operation eliminates the need for sequential processing that would accumulate higher total power consumption over time, achieving high resolution with maintained power efficiency.
Solution Approach 2:
The ramp generator and clock generator operate continuously to provide uninterrupted signals to all latch circuits simultaneously. This continuous operation eliminates idle cycles and re-initialization overhead that would increase average power consumption, allowing the ADC to maintain high resolution output with optimized power usage through sustained efficient operation.
3Measurement precision
If additional latch circuits are added to improve resolution, then the measurement precision is improved, but the device complexity increases
Solution Approach 1:
Each latch circuit is designed as a universal module that performs the same comparison and latching function independently. The first to N-th latch circuits are identical in structure and operation, allowing the complex high-resolution function to be achieved through replication of simple, standardized units rather than designing increasingly complex single-stage circuits.
Solution Approach 2:
Multiple latch circuits are merged into a unified ADC output structure where their individual results are combined to form the final high-resolution digital signal. The ramp generator and clock generator serve all latch circuits simultaneously, merging control functions to reduce the number of separate components needed and simplify the overall circuit architecture while achieving high resolution.
Data Source
AI summary
Disclosed is an analog-to-digital converter (ADC) circuit for digitizing a pixel signal into a digital signal of positive integer (N) bits. The ADC includes a ramp generator, a clock, a comparator, and a counter. A system clock signal allows the ramp generator to generate a ramp signal and the clock generator to generate first to N-th clock signals. The comparator generates a comparison signal based on a comparison of the pixel signal, received from a pixel array, and the ramp signal. The counter includes an additional latch circuit and first to N-th latch circuits. The additional latch circuit generates an additional binary signal based on the system clock signal and the comparison signal, and the first to N-th latch circuits generate first to N-th latch signals based on the comparison signal and corresponding clock signal.