Ramp ADC Reference Scaling Across Coarse and Fine Conversion
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Solution Overview
Problem
Conventional ramp analog-to-digital converters (ADCs) require a long conversion period due to the need to step through all possible digital values, which increases with resolution, leading to inaccurate digital signal generation due to differing ramp signal delivery ratios during course and fine ADC steps, affected by parasitic capacitance.
Innovation Solution
An ADC with a supply circuit that adjusts the slope of ramp signals in both stages to maintain a consistent delivery ratio, using different circuit configurations based on control signals to ensure the reference signal is scaled similarly during both stages, thereby compensating for parasitic capacitance effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a ramp ADC steps through all possible digital values to ensure correct digital output, then measurement precision is improved, but conversion time increases significantly
Solution Approach 1:
The patent divides the ADC conversion process into two distinct stages: a course conversion stage that quickly establishes an approximate digital value, and a fine conversion stage that refines the result to achieve precise digital output. This segmentation allows the system to balance conversion speed and accuracy by handling different precision requirements in separate time periods.
Solution Approach 2:
The patent dynamically adjusts the ramp signal slope based on the conversion stage. During the course conversion stage, a steeper slope is used to quickly cover the full voltage range, while during the fine conversion stage, a gentler slope is applied to achieve precise resolution. This dynamic adaptation of the ramp signal characteristics optimizes both conversion speed and precision.
2Productivity
If different ramp signal slopes are used during course and fine ADC stages, then conversion speed is improved, but measurement precision deteriorates due to differing delivery ratios
Solution Approach 1:
The patent changes the delivery ratio parameter of the ramp signal based on the conversion stage. A first delivery ratio is applied during the course conversion stage for faster conversion, while a second delivery ratio is applied during the fine conversion stage for higher precision. This parameter adaptation allows the system to optimize performance for each stage's specific requirements.
Solution Approach 2:
The patent uses feedback mechanisms to monitor and adjust the ramp signal delivery ratio during conversion. The system detects the conversion stage and automatically selects the appropriate delivery ratio to maintain precision while achieving the desired conversion speed for that particular stage.
3Device complexity
If parasitic capacitance effects are not compensated, then device complexity is reduced, but measurement precision deteriorates due to scaled ramp signals
Solution Approach 1:
The patent introduces an intermediary compensation mechanism that addresses parasitic capacitance effects without requiring complete redesign of the circuit. This intermediary solution adjusts the ramp signal characteristics to counteract the scaling effects caused by parasitic capacitance, thereby maintaining measurement precision while avoiding excessive circuit complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the conversion time and improves the accuracy of digital signal generation by maintaining a consistent ramp signal delivery ratio across stages, leading to more precise digital output.
Implementation Method 1
undesired influences like parasitic capacitance may affect the slope of the ramp signal during the course ADC step and the fine ADC differently
Data Source
AI summary
In one embodiment, an analog-to-digital converter (ADC) includes a comparator and a supply circuit. The comparator is configured to compare an input signal to a reference signal. The supply circuit is configured to supply the reference signal. The supply circuit is configured to provide different circuit configurations for supplying the reference signal during different stages of analog-to-digital conversion such that the reference signal is scaled in substantially a same manner during at least two of the stages.