Ramp ADC Control Using Multi-Sample Hold for Compact Precision
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Solution Overview
Problem
Existing semiconductor devices face a challenge in reducing circuit size while maintaining AD conversion precision, as reducing the number of AD converters degrades the quality of AD conversion.
Innovation Solution
A semiconductor device with multiple sample-and-hold circuits, a ramp signal generation circuit, a counter, comparison circuits, and a control circuit that dynamically adjust the slope of the ramp signal and counter values to optimize AD conversion precision based on input signal characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the number of AD converters is reduced to decrease circuit size, then device complexity is reduced, but AD conversion precision is degraded
Solution Approach 1:
The patent segments the AD conversion process into multiple stages: sample-and-hold circuits sample the input signal at different timings, comparison circuits compare these sampled voltages with a ramp signal at different levels, and a counter counts the comparison results. This segmentation allows the system to achieve high-precision AD conversion using simpler individual components rather than requiring multiple full AD converters, thereby reducing circuit size while maintaining precision.
Solution Approach 2:
The patent makes a single AD conversion circuit perform multiple conversion tasks by using multiple sample-and-hold circuits that sample the same input signal at different timings. This multi-functional approach allows one AD conversion pathway to handle what would traditionally require multiple separate AD converters, reducing the overall number of converters needed and thus decreasing circuit size while preserving conversion precision.
2Device complexity
If the number of AD converters is reduced to decrease circuit size, then device complexity is reduced, but conversion speed is degraded
Solution Approach 1:
The sample-and-hold circuits perform preliminary sampling of the input signal at different timings before the actual AD conversion process. This preliminary action prepares multiple voltage samples in advance, allowing the comparison and counting operations to proceed in parallel or sequential manner without waiting for sequential conversions, thereby maintaining high conversion speed even with reduced circuit complexity.
Solution Approach 2:
The patent ensures continuous useful action by having multiple sample-and-hold circuits continuously sample the input signal at different timings, and the comparison circuits continuously compare these samples with the ramp signal. This continuous operation eliminates idle time and maintains high conversion throughput, achieving fast conversion speed without requiring multiple parallel AD converter circuits.
3Measurement precision
If AD conversion precision is enhanced in all regions, then measurement precision is improved, but circuit complexity and size increase
Solution Approach 1:
The patent applies local quality by using multiple sample-and-hold circuits that sample the input signal at different timings and voltage levels, with each circuit optimized for specific signal regions. The comparison circuits then compare these locally-optimized samples with a ramp signal at appropriate levels. This localized optimization approach achieves high precision in critical signal regions without requiring excessive circuit resources across the entire conversion range, thus balancing precision with circuit size.
Data Source
AI summary
A semiconductor device includes a plurality of sample-and-hold circuits that sample voltages of an analog input signal at different timings and respectively hold them as a plurality of input voltages, a ramp signal generation circuit that generates a ramp signal whose potential changes linearly, a counter that triggers a start of the linear change in the ramp signal and perform a counting operation, a plurality of AD conversion circuits that output a count value of the counter at a timing where each of the plurality of input voltages matches the voltage of the ramp signal as a plurality of digital signals corresponding to the plurality of input voltages, and a control circuit that controls a slope of the linear change in the ramp signal and the amount of change in the count value of the counter according to the count value of the counter.