Ramp-Based Clock Synchronization for Stackable Circuits
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Solution Overview
Problem
Clock synchronization in stackable power supply circuits faces issues with high frequency synchronization causing system noise and increased power consumption, and requires complex marker pulses to indicate sequence beginnings, complicating design.
Innovation Solution
A phase generation circuit that includes a ramp generation circuit and a comparator to produce phase clock signals synchronously with a synchronization clock, eliminating the need for high frequency division and marker pulses, and allowing programmable phase selection for Master and Slave clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high frequency synchronization clock is used to generate Master and Slave clocks, then clock synchronization is achieved, but system noise and power consumption increase
Solution Approach 1:
The patent replaces the conventional high-frequency electronic clock division system with a ramp-based timing system. Instead of using high-frequency synchronization clocks and digital dividers, the invention uses a continuously rising ramp voltage signal that is compared against reference voltages to generate phase clocks. This substitution of the timing mechanism eliminates the need for high-frequency clock generation and division, thereby reducing power consumption while maintaining synchronization reliability.
Solution Approach 2:
The patent changes the fundamental parameter of clock generation from frequency-based to voltage-time based. By using a ramp signal whose voltage increases linearly with time, the system determines clock phases through voltage threshold comparisons rather than frequency division. This parameter change allows the system to achieve the same synchronization function at much lower operating frequencies, reducing power consumption and system noise.
2Reliability
If high frequency synchronization clock is used to generate Master and Slave clocks, then clock synchronization is achieved, but system noise increases
Solution Approach 1:
The patent replaces the conventional high-frequency electronic clock division system with a ramp-based timing system. Instead of using high-frequency synchronization clocks and digital dividers, the invention uses a continuously rising ramp voltage signal that is compared against reference voltages to generate phase clocks. This substitution of the timing mechanism eliminates the need for high-frequency clock generation and division, thereby reducing power consumption while maintaining synchronization reliability.
Solution Approach 2:
The patent converts the potentially harmful effect of requiring precise high-frequency timing into a beneficial low-frequency ramp-based system. By using a slowly rising ramp signal instead of high-frequency clocks, the system achieves the same phase synchronization function with dramatically reduced noise generation. The ramp signal's gradual voltage increase naturally provides precise timing references without the high-frequency switching noise inherent in conventional clock systems.
3Loss of information
If marker pulses are added to synchronization clock to indicate sequence beginning, then phase identification is improved, but device complexity increases
Solution Approach 1:
The patent extracts and eliminates the need for marker pulses from the synchronization system. Instead of adding special marker pulses to indicate sequence beginnings, the invention uses the natural starting point of the ramp signal generation as the reference point. The ramp signal begins at a known voltage level (typically zero or ground) at the start of each sequence, providing an inherent phase reference without requiring any additional marker circuitry or modified clock signals.
Solution Approach 2:
The ramp-based system is self-sufficient in providing phase identification. The ramp signal automatically provides timing references at all phase points through its continuous voltage increase. Each phase clock is generated by comparing the ramp signal against appropriately set reference voltages, eliminating the need for external marker pulses or complex phase identification circuitry. The system serves its own timing and synchronization needs through the inherent properties of the ramp waveform.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution simplifies and flexibly generates Master and Slave clocks, reducing power consumption and system noise, and simplifies printed circuit board design by eliminating the need for high frequency synchronization and marker pulses.
Implementation Method 1
a ramp generation circuit arranged to generate a ramp signal in synchronization with a synchronization clock signal
Implementation Method 2
The comparator has a first input terminal coupled to receive the ramp signal and a second input terminal coupled to receive the reference signal. The comparator produces a phase clock signal at an output terminal.
Data Source
AI summary
A phase generation circuit is disclosed. The circuit includes a ramp generation circuit arranged to generate a ramp signal in synchronization with a synchronization clock signal. A phase selection circuit generates a reference signal in response to a phase selection signal. A comparator has a first input terminal coupled to receive the ramp signal and a second input terminal coupled to receive the reference signal. The comparator produces a phase clock signal at an output terminal.