Ramp-Generator Delay Circuit for Stable MRAM Timing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing delay circuits for MRAM are sensitive to variations in temperature and power supply voltage, leading to inconsistent delays in read and write operations.
Innovation Solution
A delay circuit comprising a ramp generator circuit and a first inverter, where the ramp generator circuit includes a capacitor charged or discharged by a current source, and a digital control signal adjusts the current sources to control the delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional delay circuits are used for MRAM operations, then the circuit structure is simple, but the delay is sensitive to temperature and power supply voltage variations
Solution Approach 1:
The patent changes the operating parameters of the inverter circuit by introducing a controllable current source that adjusts the switching threshold voltage. This allows the delay circuit to maintain stable operation across temperature and power supply variations by dynamically adjusting the voltage parameter at which the inverter switches states
Solution Approach 2:
The patent introduces an intermediate control circuit that includes a current source and associated switching elements. This intermediary circuit mediates between the power supply and the inverter, providing controlled current that stabilizes the inverter's switching behavior against environmental variations
2Adaptability or versatility
If fixed delay circuits are used, then the circuit design is simple, but the delay time cannot be adjusted for different MRAM operations
Solution Approach 1:
The patent transforms the static delay circuit into a dynamic one by introducing controllable current sources that can be adjusted during operation. The current magnitude is controlled by digital signals, allowing the delay time to be dynamically adjusted to match different MRAM operation requirements (read, write, erase)
Solution Approach 2:
The patent designs a universal delay circuit that can serve multiple MRAM operations (read, write, erase) by adjusting the current control signals. The same basic circuit structure handles different delay requirements through programmable current adjustment, eliminating the need for separate fixed-delay circuits for each operation type
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The circuit provides a controllable and stable delay that is less sensitive to temperature and power supply variations, enabling precise timing for MRAM operations without relying on an external clock.
Implementation Method 1
The ramp generator circuit includes a capacitor, electrically coupled to the input of the first inverter
Implementation Method 2
a first current source, electrically coupled in series between a power supply conductor and a power supply connection of the two power supply connections of the first inverter
Data Source
AI summary
A delay circuit. In some embodiments, a non-transitory computer readable medium includes stored instructions, which when executed by a processor, cause the processor to generate a digital representation of a circuit including: a first inverter, having an input, an output, and two power supply connections; a first current source, electrically coupled in series between a power supply conductor and a power supply connection of the two power supply connections of the first inverter; and a ramp generator circuit, electrically coupled to the input of the first inverter.