Ramp-Based Delay Circuit for Supply Noise Immunity
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Solution Overview
Problem
Conventional delay circuits in electronic applications are prone to noise interference from parasitic inductances, leading to random failures and requiring costly layout design revisions, which is particularly critical in applications like autonomous vehicles where reliability is paramount.
Innovation Solution
A noise-tolerant delay circuit design that excludes memory elements, utilizing a reference current generator and inverting delay stages with transistors and capacitors to generate ramp signals, ensuring the delay time period is independent of supply voltage and temperature, thereby reducing the impact of noise fluctuations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional delay circuits use current controlled ramp signals with comparators and reference voltages or oscillators to create pulses using latches, counters, and decoders, then the delay circuit can generate fast edges with relatively short time periods, but noise in the ground voltage or supply voltage can cause fluctuations in signal state that result in latching false or incorrect states, leading to random changes in functionality and circuit failure
Solution Approach 1:
The patent removes memory elements (latches, counters, decoders) from the delay circuit, extracting the problematic component that causes noise susceptibility. The delay function is achieved purely through passive RC timing networks and simple switching transistors, eliminating the feedback loops and state-latching mechanisms that amplify noise effects.
Solution Approach 2:
The patent changes the operating parameters by using supply voltage-independent delay generation through carefully designed RC networks where the delay time is determined by resistor and capacitor values rather than by voltage levels or frequency-dependent oscillators, making the circuit immune to supply noise fluctuations.
2Measurement precision
If conventional delay circuits use memory elements such as latches, counters, and decoders, then the circuit can generate precise delay signals, but the circuit becomes susceptible to noise-induced state fluctuations and random functionality changes
Solution Approach 1:
The patent converts the harmful effect of noise by designing a circuit where noise fluctuations cannot affect the delay time. The RC networks are designed such that the delay is determined by physical component values (R and C) rather than electrical states that can be flipped by noise, effectively using the noise immunity of passive components to protect against the harmful effects that plague active memory elements.
3Reliability
If circuit layout on a printed circuit board is designed to handle parasitic inductances between components, then the circuit can achieve better noise immunity, but the layout design requires several costly and time-consuming revisions
Solution Approach 1:
The patent extracts the problematic interaction between parasitic inductances and memory elements by removing the memory elements entirely. Since the delay circuit uses simple RC networks without feedback loops or state-latching components, parasitic inductances in the PCB layout do not cause oscillations or state flips, dramatically simplifying layout requirements.
4Device complexity
If the delay time period depends on supply voltage and temperature, then the circuit can be simpler to design, but the delay varies significantly under varying operating conditions
Solution Approach 1:
The patent changes the dependency parameters by designing RC networks where the delay time is determined by physical resistor and capacitor values rather than by supply voltage or temperature-dependent device characteristics. This is achieved through careful selection of R and C values and circuit topologies that minimize voltage and temperature coefficients.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed delay circuit achieves robustness against noise, simplifying circuit layout and reducing design complexities, ensuring reliable operation across varying conditions without significant changes in delay time periods despite supply voltage fluctuations.
Implementation Method 1
The first set of transistors forms a first current source when activated. The first current source generates a first current about equal to the reference current and is electrically connected to the capacitor to generate a ramp signal with a positive slope by charging the capacitor with the first current
Implementation Method 2
The input set of transistors inverts an input signal to produce an inverted input signal. The first set of transistors forms a first current source when activated. The second set of transistors forms a second current source when activated.
Implementation Method 3
The first bias transistor causes the ramp signal to be biased to a ground voltage when the first set of transistors is activated at a start of the first time period, which causes the ramp signal to ramp up during the first time period from the ground voltage towards the supply voltage
Data Source
AI summary
In a delay circuit, first and second sets of transistors are connected in series between a supply voltage and a ground. The first and second sets of transistors both include a current source transistor, a cascode transistor, and a control transistor. The first set of transistors generates a current that charges a capacitor to generate a ramp signal with a positive slope. A first bias transistor may cause the ramp signal to be biased to ground upon activating the first set of transistors. The second set of transistors generates a current that discharges the capacitor to generate the ramp signal with a negative slope. A second bias transistor may cause the ramp signal to be biased to the supply voltage upon activating the second set of transistors. The delay circuit transitions the state of the output signal based on a voltage level of the ramp signal.