Ramp-Based Delay Circuit for Noise-Tolerant Timing
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Solution Overview
Problem
Conventional delay circuits in electronic applications are prone to noise interference from parasitic inductances, leading to random failures and requiring costly layout design revisions, which can be catastrophic in critical applications like autonomous vehicles.
Innovation Solution
A noise-tolerant delay circuit design that excludes memory elements, utilizing a reference current generator and inverting delay stages with transistors and capacitors to generate ramp signals, ensuring the delay time is independent of supply voltage and temperature, thereby reducing the impact of noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional delay circuits use memory elements (latches, counters, decoders) to generate delayed signals, then the delay function is achieved, but noise in ground voltage or supply voltage causes fluctuations in signal state leading to random failures
Solution Approach 1:
The patent removes memory elements (latches, counters, decoders) from the delay circuit, extracting the problematic component that causes noise susceptibility. The delay function is achieved through a simpler RC-based timing circuit without any memory elements, thereby eliminating the source of noise-induced random failures while maintaining the core delay functionality.
Solution Approach 2:
The patent uses a simple RC timing circuit with resistors and capacitors instead of complex memory elements. These passive components are inherently more noise-tolerant and do not have the state-latching behavior that causes random failures. The circuit uses basic, inexpensive components that are less susceptible to noise interference.
2Reliability
If conventional delay circuits are designed to be noise-tolerant, then reliability improves, but costly and time-consuming layout design revisions are required to deal with parasitic inductances
Solution Approach 1:
By removing memory elements from the circuit, the patent eliminates the components that are most susceptible to noise and parasitic inductances. This extraction simplifies the layout requirements, as the remaining RC timing circuit and current sources are much less sensitive to parasitic effects, reducing the need for costly layout revisions.
Solution Approach 2:
The patent changes the operational parameters of the delay circuit by using current-controlled RC timing instead of memory element state transitions. This parameter change makes the circuit inherently more tolerant to parasitic inductances and noise, allowing for more relaxed layout design constraints without sacrificing reliability.
3Ease of operation
If delay circuits use current controlled ramp signals with comparators and reference voltages, then delay functionality is achieved, but the circuit becomes susceptible to noise-induced state fluctuations
Solution Approach 1:
The patent replaces expensive and noise-sensitive comparators and reference voltage circuits with simpler RC timing circuits. The delay is achieved through the natural charging and discharging of capacitors through resistors, which is inherently more noise-tolerant. This substitution maintains the delay function while significantly reducing noise susceptibility.
Solution Approach 2:
The patent converts the harmful effect of noise by using a circuit topology where the delay mechanism (RC charging/discharging) is inherently less susceptible to noise than the alternative (comparator-based memory elements). The noise that would affect comparators and reference voltages has minimal impact on the RC timing waveform, effectively converting the noise vulnerability of one approach into the robustness of another.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed delay circuit significantly reduces noise susceptibility, allowing for more robust and reliable operation across varying conditions without the need for extensive layout revisions, enhancing the reliability of critical systems.
Implementation Method 1
The first current source is electrically connected to a capacitor to generate a ramp signal with a positive slope by charging the capacitor with the first current
Implementation Method 2
The first set of transistors forms a first current source when activated. The first current source generates a first current about equal to the reference current
Data Source
AI summary
In a delay circuit, first and second sets of transistors are connected in series between a supply voltage and a ground. The first and second sets of transistors both include a current source transistor, a cascode transistor, and a control transistor. The first set of transistors generates a current that charges a capacitor to generate a ramp signal with a positive slope. A first bias transistor may cause the ramp signal to be biased to ground upon activating the first set of transistors. The second set of transistors generates a current that discharges the capacitor to generate the ramp signal with a negative slope. A second bias transistor may cause the ramp signal to be biased to the supply voltage upon activating the second set of transistors. The delay circuit transitions the state of the output signal based on a voltage level of the ramp signal.