Ramp Generator Fine Gain Using Fractional Divider Modulation
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Solution Overview
Problem
Image sensors face limitations in achieving high resolution analog fine gain with limited fine gain adjustment steps, leading to significant gain errors, especially at higher gain values, due to the restricted number of fine gain adjustment steps in traditional ramp generators.
Innovation Solution
The implementation of a ramp generator using a fractional divider with a delta-sigma modulator, which allows for ultra-high resolution fine gain adjustments by adjusting the fractional divider ratio, thereby providing a higher number of fine gain steps without increasing power consumption or chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional ramp generators with limited fine gain adjustment steps are used, then device complexity is reduced, but measurement precision deteriorates due to significant gain errors
Solution Approach 1:
The patent changes the parameter of fine gain adjustment from discrete steps to continuous adjustment by modifying the fractional divider ratio. This allows the ramp generator to achieve ultra-high resolution fine gain (e.g., 1/220 resolution) by continuously varying the divider ratio parameter, thereby eliminating the gain errors associated with limited discrete steps while avoiding increased device complexity.
Solution Approach 2:
The patent introduces dynamic adjustment capability to the ramp generator by implementing a fractional divider with delta-sigma modulator that can dynamically change the divider ratio. This dynamic mechanism enables real-time fine gain adjustment without requiring multiple fixed gain stages, thus improving measurement precision while maintaining simple device architecture.
2Measurement precision
If more fine gain adjustment steps are added to improve gain precision, then measurement precision improves, but device complexity and chip area increase
Solution Approach 1:
The patent makes the fractional divider circuit universal by designing it to perform multiple functions: it serves as both the clock division mechanism and the fine gain adjustment mechanism. By adjusting the fractional divider ratio, the same circuit achieves ultra-high resolution fine gain without requiring separate dedicated circuits for each function, thereby improving fine gain resolution without increasing chip area.
Solution Approach 2:
The patent replaces the traditional mechanical approach of adding more physical gain adjustment stages with an electronic/software-based fractional divider ratio adjustment. This substitution allows ultra-high resolution fine gain to be achieved through digital control of the fractional divider, eliminating the need for additional physical components and reducing chip area while maintaining high measurement precision.
3Measurement precision
If more fine gain adjustment steps are added to reduce gain errors, then measurement precision improves, but power consumption increases
Solution Approach 1:
The patent achieves ultra-high resolution fine gain and reduced gain errors by changing the operational parameter of the fractional divider ratio rather than increasing the number of active circuit stages. This parameter-based approach allows fine gain adjustment without activating additional power-consuming components, thereby improving gain accuracy while maintaining low power consumption.
Solution Approach 2:
The fractional divider circuit serves itself by using its own ratio adjustment mechanism to achieve fine gain control. The delta-sigma modulator within the fractional divider automatically adjusts the division ratio to achieve the desired fine gain, eliminating the need for external control circuits that would consume additional power, thus improving gain accuracy without increasing overall power consumption.
Data Source
AI summary
A ramp generator providing ramp signal with high resolution fine gain includes a current mirror having a first and second paths to conduct a capacitor current and an integrator current responsive to the capacitor current. First and second switched capacitor circuits are coupled to the first path. A fractional divider circuit is coupled to receive a clock signal to generate in response to an adjustable fractional divider ratio K a switched capacitor control signal that oscillates between first and second states to control the first and second switched capacitor circuits. The first and second switched capacitor circuits are coupled to be alternatingly charged by the capacitor current and discharged in response to each the switched capacitor control signal. An integrator coupled is to the second path to generate the ramp signal in response to the integrator current.