Ramp Signal Generator Feedback Circuit for Low-INL Image Sensors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing ramp signal generators suffer from integral non-linearity (INL) issues due to switch transistors operating in a triode region at the beginning of the ramping period, leading to errors in ramp signal linearity and deteriorated image quality.
Innovation Solution
A ramp signal generator design that includes a negative feedback circuit to maintain a constant voltage at the switching node by controlling the gate terminal of a first transistor, ensuring it operates in a saturation region, thereby reducing current flow through a load resistor and maintaining a consistent slope.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If switch transistors operate in triode region at the beginning of ramping period, then current can flow freely through the circuit, but integral non-linearity (INL) performance deteriorates and ramp signal linearity errors occur
Solution Approach 1:
A negative feedback circuit is introduced that monitors the voltage at the switching node and adjusts the gate terminal voltage of the first transistor accordingly. This feedback mechanism ensures the transistor operates in the saturation region throughout the ramping period, maintaining constant current flow through the load resistor and eliminating INL errors while preserving high-speed operation.
Solution Approach 2:
The operating region of the switch transistor is changed from triode region to saturation region through controlled parameter adjustment. By maintaining the transistor in saturation region, the current becomes independent of voltage variations, ensuring linear ramp signal generation with constant slope and improved INL performance.
2Manufacturing precision
If negative feedback circuit is added to maintain constant voltage at switching node, then INL characteristics improve and ramp signal linearity is maintained, but device complexity increases
Solution Approach 1:
The negative feedback circuit is designed with minimal components that monitor the switching node voltage and provide corrective control to the transistor gate. This approach achieves improved INL performance through a relatively simple feedback mechanism that does not significantly increase overall device complexity.
3Manufacturing precision
If transistor operates in saturation region throughout ramping period, then ramp signal linearity is maintained with constant slope, but current control complexity increases
Solution Approach 1:
The negative feedback circuit automatically adjusts the gate voltage to maintain saturation region operation, eliminating the need for complex external current control mechanisms. The feedback loop handles the complexity internally, ensuring consistent current flow and linear ramp signal generation.
Solution Approach 2:
The circuit uses its own output voltage to control its operation through the feedback mechanism. The switching node voltage directly influences the gate terminal voltage, creating a self-regulating system that maintains saturation region operation and consistent current flow without external intervention.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Improves INL characteristics by maintaining a constant voltage at the switching node, preventing errors in ramp signal linearity and ensuring high-speed operation without deteriorating image quality.
Implementation Method 1
a negative feedback circuit that maintains a constant voltage at the first switching node by controlling a gate terminal of the first transistor based on a voltage of the first switching node
Implementation Method 2
a first transistor connected between a first switching node and the output node, the cell current flowing to the resistor through the first transistor
Data Source
AI summary
A ramp signal generator includes a resistor connected between an output node outputting a ramp signal that increases or decreases at a constant slope and a first power node which receives a first power voltage, and plural current cells. A cell current flows through each of the current cells to the first power node or the resistor. The current cells include a first current cell. The first current cell includes a first transistor connected between a first switching node and the output node, the cell current flowing to the resistor through the first transistor, a second transistor connected between the first switching node and the first power node, the cell current flowing to the first power node through the second transistor, and a negative feedback circuit that maintains a constant voltage at the first switching node.


