Ramp-Linearized Digital-to-Time Converter for Low-Noise PLLs
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Solution Overview
Problem
Existing digital-to-time converters (DTCs) in wireless communication devices suffer from non-linear transfer functions, which lead to increased quantization noise and power consumption, affecting the performance of phase locked loops (PLLs) in terms of phase noise and settling time.
Innovation Solution
The implementation of a digital-to-time converter apparatus comprising an input buffer, a ramp voltage generator, an evaluation circuit with a series-connected resistor and FET, and an output buffer, which generates a ramp voltage and output voltage with inverse transfer functions to linearize the delay response and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional digital-to-time converter is used in a phase locked loop, then the device can operate, but quantization noise is not sufficiently reduced and linearity is poor
Solution Approach 1:
The patent transforms the conventional digital-to-time converter into a digital-to-analog converter by changing the output parameter from direct time delay to ramp voltage generation. The DTC code controls the ramp voltage slope or intersection point, converting discrete digital steps into continuous analog voltage variations that can be precisely linearized through circuit design rather than algorithmic correction.
Solution Approach 2:
The patent introduces an intermediary analog voltage domain between the digital input code and the final time delay output. The ramp voltage generator creates an analog intermediate signal that mediates the conversion process, allowing linearization to be achieved through analog circuit characteristics rather than direct digital processing, thereby reducing quantization noise inherent in purely digital approaches.
2Speed
If the loop filter bandwidth is increased to improve response speed, then settling time is reduced, but phase noise performance deteriorates
Solution Approach 1:
The patent changes the fundamental operating parameter of the DTC from direct time delay control to ramp voltage generation. This parameter change enables the system to achieve faster settling by using voltage ramping mechanisms that can respond more quickly to frequency changes, while the analog nature of the ramp voltage allows for better noise filtering that prevents phase noise deterioration even with increased loop bandwidth.
3Measurement precision
If a linearized DTC response is achieved through complex correction circuits, then linearity improves, but device complexity increases
Solution Approach 1:
The patent achieves linearization by changing the fundamental parameter from direct time delay to ramp voltage generation. This single parameter change inherently provides linear response characteristics through the controlled charging or discharging of capacitors with constant current, eliminating the need for complex correction circuits while maintaining high linearity.
Solution Approach 2:
The patent extracts the linearization function from complex digital correction logic and implements it through simple analog ramp voltage generation. By taking out the need for complex feedback and correction circuits, the design achieves high linearity through the natural linear characteristics of capacitor charging/discharging processes, significantly reducing overall circuit complexity.
Data Source
AI summary
An aspect relates to an apparatus including an input buffer including an input configured to receive an input voltage; a ramp voltage generator including an input coupled to an output of the input buffer; an evaluation circuit including an input coupled to an output of the ramp voltage generator, wherein the evaluation circuit includes a first resistor coupled in series with first field effect transistor (FET) between a first voltage rail and a second voltage rail; and an output buffer including an input coupled to a drain of the first FET and an output configured to generate an output voltage.