Ramp Rate Control for Large Scale Computing Power Spikes
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Solution Overview
Problem
Large-scale computing systems experience undesirable power spikes and abrupt transitions during application launch, runtime, and exit due to simultaneous node operations, leading to potential system failures and contractual violations related to power consumption.
Innovation Solution
A ramp rate control tool that oversees processor transitions and manages power consumption by controlling processor states, using stepped transitions and randomized sleep times to smooth power changes, and limiting deepest C-State usage, coordinated by workload managers to avoid sudden power spikes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If nodes transition from idle to active state simultaneously at application launch, then application execution speed is improved, but power consumption spikes dramatically
Solution Approach 1:
The patent segments the simultaneous node activation process into multiple phased stages. Nodes are activated in batches rather than all at once, with each batch transitioning through intermediate power states (C-states) before reaching full operational capacity. This segmentation of the activation process spreads the power demand over time while still achieving rapid application execution.
Solution Approach 2:
The system performs preliminary actions by pre-warming or pre-activating a subset of nodes before the main application launch. This preliminary activation creates a staged approach where nodes are progressively brought online, reducing the instantaneous power spike while ensuring computational resources are ready for rapid application execution.
2Loss of energy
If nodes remain in deepest C-State to minimize power consumption, then energy efficiency is improved, but transition to active state causes abrupt power spikes
Solution Approach 1:
The patent implements periodic action by introducing controlled delays and intermediate states between the deepest C-State and full operational state. Nodes transition through a sequence of C-states (e.g., C6→C3→C1→C0) with staged activation intervals, creating a periodic pattern that smooths power transitions while maintaining energy efficiency during idle periods.
Solution Approach 2:
The system changes the power state parameters progressively rather than making abrupt transitions. By adjusting C-State levels in stages and controlling the timing of state transitions, the patent modifies the power consumption parameters to avoid spikes while maintaining the ability to rapidly activate when needed.
3Productivity
If all constituent parts of parallel applications reach synchronization barriers simultaneously, then application throughput is improved, but power consumption swings dramatically
Solution Approach 1:
The patent segments the synchronization process by introducing staggered timing for different constituent parts of parallel applications. Instead of all parts reaching barriers simultaneously, they are coordinated to arrive in phases, which maintains overall application throughput while distributing the power demand across multiple smaller transitions rather than one large swing.
4Productivity
If multiple nodes are activated simultaneously to support large application launch, then application performance is improved, but contractual power obligations may be violated
Solution Approach 1:
The system performs preliminary power management actions by pre-coordinating node activation schedules and establishing phased startup sequences before application launch. This preliminary planning ensures that power consumption remains within contractual obligations while still providing sufficient computational resources for high-performance application execution.
Solution Approach 2:
The patent adjusts power consumption parameters dynamically during the activation process, modifying node activation timing and C-State transition rates to keep power usage within contractual limits. By changing these parameters in a coordinated manner, the system maintains both performance and compliance.
Data Source
AI summary
To eliminate the adverse effects of power swings in a large scale computing system during the life cycle of an application or job, control of several operating characteristics for the collective group of processors is provided. By providing certain levels of coordination for the many processors utilized in large scale computing systems, significant and abrupt changes in power needs can be avoided. In certain circumstances, this may involve limiting the transition between several C-States of the processors involved and the overall power transitions for a large scale system are not detrimental and do not create issues for the data center or local power utility. Some cases will require stepped transitions between C-States, while other cases will include both stepped and modulated transitions. Other cases will incorporate random wait times at the various transitions in order to spread the power consumption involved. In yet further circumstances the C-States can be pinned to a specific setting, thus avoiding transitions caused by C-State transitions. To deal with further issues, the processor P-States can also be overridden.