Ramp-Stack Chip Package With Microspring Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing chip packaging techniques, such as wire bonding and through-silicon vias (TSVs), face challenges in achieving high bandwidth and low cost while minimizing silicon area consumption and processing complexity.
Innovation Solution
A chip package design featuring a stack of semiconductor dies with offset configuration and a ramp component electrically and mechanically coupled using microsprings and mechanical stops, eliminating the need for TSVs and allowing for high-bandwidth communication without area-consuming vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If through-silicon vias (TSVs) are used to connect stacked chips, then inter-component communication bandwidth is improved, but silicon area consumption increases significantly
Solution Approach 1:
The patent transitions from planar TSV connections to a three-dimensional ramp structure that connects stacked chips at an angle. The ramp component extends diagonally through the stack, allowing electrical connections to be made at multiple heights without requiring vertical vias through the entire silicon thickness. This dimensional approach reduces the footprint on each chip layer while maintaining high bandwidth communication paths.
Solution Approach 2:
The connection structure is divided into multiple ramp segments that connect adjacent chips in the stack. Instead of a single through-silicon via penetrating the entire stack, the connection is segmented into multiple shorter ramp portions, each connecting to a specific chip layer. This segmentation allows for optimized local connections and reduces the overall silicon area required for interconnect structures.
2Speed
If through-silicon vias (TSVs) are used to connect stacked chips, then inter-component communication bandwidth is improved, but manufacturing cost increases
Solution Approach 1:
The ramp structures are pre-formed on separate substrates before the chip stacking process. The ramps are created using standard semiconductor fabrication techniques on dedicated interconnect layers, allowing for parallel processing and optimization. This preliminary formation of connection structures separates the interconnect fabrication from the chip manufacturing, enabling independent optimization and reducing overall manufacturing complexity and cost.
Solution Approach 2:
The ramp component serves as an intermediary structure between the stacked chips, providing a dedicated interconnect layer that mediates the electrical connections. This intermediary ramp structure allows for standardized connection interfaces and simplifies the bonding process between chips, as the ramps provide pre-configured electrical pathways that eliminate the need for complex through-silicon via formation and alignment procedures.
3Reliability
If chips are stacked with offset configuration, then mechanical coupling and electrical connection are improved, but alignment precision requirements increase
Solution Approach 1:
The ramp structures incorporate curved or angled geometries that naturally guide alignment during the stacking process. The diagonal orientation of the ramps creates a tapered entry point that facilitates self-alignment as chips are bonded together, reducing the sensitivity to initial positioning errors. The curved profile of the ramps provides mechanical guidance that maintains alignment precision while accommodating minor variations in chip placement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces costs and silicon area usage, offers high inter-component communication bandwidth, and facilitates reworkability by avoiding TSV-related processing overheads and area consumption, while maintaining reliability and efficiency.
Implementation Method 1
The ramp component is electrically coupled to each of the semiconductor dies by microsprings
Implementation Method 2
mechanically coupled to each of the semiconductor dies by mechanical stops, which are formed on respective semiconductor dies for mechanical contact between the semiconductor dies and the ramp component
Data Source
Figure 1A
Figure 1B
Figure 2A
AI summary
A chip package is described (450). This chip package includes a stack of semiconductor dies (110-1,110-2,110-N) or chips that are offset from each other, thereby defining a terrace with exposed pads. A ramp component (112), which is positioned approximately parallel to the terrace, electrically couples to the exposed pads. Mechanical stops (460-1) are formed on respective semiconductor die for mechanical contact between the semiconductor die and the ramp component. The ramp component is electrically coupled to the semiconductor dies using microsprings (114). Consequently, the electrical contacts may have a conductive, a capacitive or, in general, a complex impedance. By removing the need for costly and area-consuming through-silicon vias (TSVs) in the semiconductor dies, the chip package facilitates chips to be stacked in a manner that provides high bandwidth and low cost.