Ramp-stack chip package with offset dies and terraced pads
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Solution Overview
Problem
Existing chip packaging methods, such as wire bonding and through-silicon vias (TSVs), face challenges of high cost and area consumption, limiting the efficiency and bandwidth of stacked semiconductor chip packages.
Innovation Solution
A chip package design featuring a stack of semiconductor dies with offset configuration and a ramp component, utilizing two rows of pads for electrical and mechanical coupling without through-chip vias, allowing for high-bandwidth communication and reduced cost by eliminating the need for TSVs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If through-silicon vias (TSVs) are used to connect stacked chips, then bandwidth is improved, but chip area is consumed and cost increases
Solution Approach 1:
The patent transitions from planar pad arrangements to a three-dimensional stepped terrace configuration. Chips are offset vertically and horizontally to create multiple elevation levels, allowing pads to be arranged on terraced surfaces rather than flat planes. This dimensional change enables increased bandwidth without proportionally increasing chip area consumption.
Solution Approach 2:
The pad structure is segmented into multiple rows and levels corresponding to different chip stacks. Each terrace level contains pads organized in rows that align with specific chip positions, allowing independent optimization of connection paths for different chip layers without interfering with other connections.
2Speed
If through-silicon vias (TSVs) are used to connect stacked chips, then bandwidth is improved, but manufacturing cost increases
Solution Approach 1:
The patent extracts the need for through-silicon vias by implementing an alternative connection architecture using offset chip stacking and terraced pad arrangements. This eliminates the costly TSV fabrication process while maintaining high bandwidth through direct pad-to-pad connections on stepped surfaces.
3Adaptability or versatility
If chips are stacked offset to define a stepped terrace, then connection flexibility is improved, but alignment precision requirements increase
Solution Approach 1:
Alignment features such as protrusions and recesses are pre-formed on chips before stacking. These features guide precise positioning during assembly, ensuring that offset chips align correctly with their corresponding pads on terraced levels without requiring complex real-time adjustment mechanisms.
Data Source
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AI summary
A chip package includes a stack of semiconductor dies or chips that are offset from each other, thereby defining a terrace with exposed pads. Surfaces of each of the semiconductor dies in the stepped terrace include two rows of first pads approximately parallel to edges of the semiconductor dies. The chip package includes a high-bandwidth ramp component, which is positioned approximately parallel to the terrace, and which has a surface that includes second pads arranged in at least two rows of second pads for each of the semiconductor dies. The second pads are electrically and mechanically coupled to the exposed first pads by connectors. The electrical contacts in the chip package may have a conductive, a capacitive or, in general, a complex impedance. The chips and/or the ramp component may be positioned relative to each other using a ball-and-pit alignment technique.