Ramp Timer Circuit With Pulse Reset to Cut Comparator Dead Time
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Solution Overview
Problem
Existing timer circuits with comparator-based time base generation suffer from parasitic dead time due to the comparator's switching time contributing twice, leading to inefficiencies and fluctuations in the ramp voltage profile.
Innovation Solution
The proposed timer circuit utilizes the comparator only once to mark the beginning of the time duration, with an additional voltage pulse generator circuit defining the end of the reset signal independently, thereby minimizing parasitic effects and improving precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the comparator is used to define both the start and end of the reset signal, then the time base generation is simplified, but the dead time increases due to the comparator's switching time contributing twice
Solution Approach 1:
The patent segments the reset signal generation into two independent parts: the start is defined by the comparator output, and the end is defined by a separate voltage pulse generator circuit. This segmentation allows each component to optimize its function without the other's parasitic effects, specifically reducing the dead time caused by comparator switching delays.
Solution Approach 2:
The patent introduces an intermediary voltage pulse generator circuit that acts as a mediator between the comparator output and the reset signal. This intermediary circuit generates a precise voltage pulse with a defined duration that is independent of the comparator's reset time, thereby eliminating the parasitic dead time contribution from the comparator.
2Device complexity
If the comparator's reset time duration is used to define the end of the reset signal, then the circuit structure is simpler, but the time precision deteriorates due to process-dependent fluctuations
Solution Approach 1:
The patent extracts the time duration definition function from the comparator's intrinsic reset time and transfers it to a dedicated voltage pulse generator circuit. This extraction allows the time base precision to be determined by stable, definable parameters (capacitance and charging current) rather than by the comparator's process-dependent reset time fluctuations.
Solution Approach 2:
The patent changes the determining parameters of the reset signal duration from the comparator's switching characteristics (which are process-dependent and fluctuating) to the voltage pulse generator's capacitance and charging current (which are stable and precisely definable). This parameter change improves time base precision while maintaining circuit functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the dead time in the ramp voltage generator, enhances the precision of the time base generation, and allows for more stable and definable parameters, such as capacitance and charging current, to determine the time base length.
Implementation Method 1
a constant-current source 104 in order to charge a capacitor 106/C1
Implementation Method 2
A voltage difference between a present voltage value vramp and a reference voltage vref can be monitored by means of a comparator 102
Data Source
AI summary
A timer circuit including a ramp voltage generator configured to generate a ramp voltage, a comparator coupled on its input side to the ramp voltage generator to receive the ramp voltage and configured to compare the ramp voltage with a switching threshold, and a voltage pulse generating circuit configured to generate a reset signal as a response to a received output signal of the comparator, wherein the reset signal has a shorter time duration than an intrinsic reset time duration of the comparator.