Ramp Voltage Generator Slope Mismatch Correction
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Solution Overview
Problem
Conventional image sensing devices face a mismatch between coarse and fine ramp voltages, leading to linearity errors and erroneous digital signal outputs due to fabrication mismatches, which affect the performance of 2-step ADCs.
Innovation Solution
A ramp voltage generator that includes a correction block to generate slope correction signals, a common bias voltage generation block, and separate ramp voltage generation blocks for coarse and fine conversion periods, allowing for the adjustment of ramp voltage slopes to compensate for mismatches and improve linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If separate bias voltages are used for coarse and fine ramp voltage generation blocks, then each block can be independently optimized, but fabrication mismatches cause slope inconsistencies between the two blocks
Solution Approach 1:
The patent merges the bias voltage generation for coarse and fine ramp voltage blocks into a single common bias voltage generation block. This ensures that both coarse and fine ramp voltages are generated from the same bias voltage source, eliminating fabrication mismatches between separate bias voltage blocks while maintaining independent optimization capability through separate control signals.
Solution Approach 2:
The common bias voltage generation block serves multiple functions by providing the bias voltage to both coarse and fine ramp voltage generation blocks simultaneously. This multi-functional approach ensures consistent slope characteristics across different conversion stages while maintaining the ability to independently control each stage's operation.
2Device complexity
If a single-slope ADC is used, then the circuit structure is simple, but the readout time is excessively long requiring a clock cycle of 2^10=1024
Solution Approach 1:
The patent segments the ADC conversion process into two distinct stages: coarse conversion using a first ramp voltage for the most significant bits, and fine conversion using a second ramp voltage for the least significant bits. This segmentation reduces the total readout time from 1024 clock cycles to 136 clock cycles while maintaining relatively simple circuit structures in each stage.
Solution Approach 2:
The patent dynamically switches between different ramp voltage slopes appropriate for different conversion stages. The coarse conversion uses a slower slope suitable for settling, while the fine conversion uses a faster slope to complete the remaining bits quickly, optimizing both accuracy and speed throughout the conversion process.
3Productivity
If a 2-step ADC is used to reduce readout time, then the readout time is effectively reduced compared to single-slope ADC, but slope mismatches between coarse and fine ramp voltages cause linearity errors
Solution Approach 1:
By merging the bias voltage sources into a single common block, the patent ensures that both coarse and fine ramp voltages originate from the same reference, eliminating fabrication-induced slope mismatches. This maintains measurement precision while preserving the fast readout speed advantage of the 2-step architecture.
4Adaptability or versatility
If different bias voltages are applied to coarse and fine ramp voltage generation blocks, then each block can operate independently, but mismatched slopes lead to erroneous digital signal outputs
Solution Approach 1:
The common bias voltage generation block provides universal biasing for both coarse and fine conversion blocks, ensuring consistent slope characteristics across different operational modes. This maintains reliability and accuracy while preserving the adaptability to handle different conversion requirements through separate control mechanisms.
Data Source
AI summary
A ramp voltage generator may include: a correction block suitable for generating a slope correction signal for first and second periods based on a period signal for distinguishing the periods; a common bias voltage generation block suitable for generating a common bias voltage based on the slope correction signal and a source bias voltage; and a first ramp voltage generation block suitable for generating a first ramp voltage having a predetermined slope during the first period based on the common bias voltage and a first ramp group control signal; and a second ramp voltage generation block suitable for generating ramp voltages having the predetermined slope during the second period based on the common bias voltage and a second ramp group control signal.