Ramped Gate Erase for Dual Bit Flash Memory
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Solution Overview
Problem
Flash memory devices face challenges with long programming and erasing times, over-erasing issues, and increased power consumption, particularly due to the interdependency of complementary bits which can lead to errors and reduced device reliability as the channel length decreases.
Innovation Solution
A ramped voltage gate erasure technique is employed, starting with a lower initial voltage and incrementally increasing it to efficiently erase dual bit flash memory sectors with fewer pulses, reducing power consumption and improving reliability over traditional fixed voltage methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional fixed voltage erase method is used, then erase operation can be performed, but the number of pulses required is large and power consumption is high
Solution Approach 1:
The patent applies dynamics by transitioning from a static fixed voltage erase method to a dynamic ramped voltage method. The control gate voltage is gradually increased from an initial lower voltage to a final higher voltage over multiple pulses, allowing the erase operation to adapt to the memory cell's erasure progress and reduce both time and power consumption.
Solution Approach 2:
The patent changes the voltage parameter dynamically during the erase operation. Instead of applying a constant high voltage, the control gate voltage is ramped up incrementally across multiple pulses, optimizing the balance between erase effectiveness, speed, and power consumption.
2Quantity of substance
If channel length is decreased to increase storage density, then packing density improves, but complementary bit interdependency increases causing errors
Solution Approach 1:
The patent applies local quality by selectively applying different voltage levels to different regions of the memory array during erase operations. By using wordline-selective ramped voltage erasure, only specific blocks or sectors are erased at a time with optimized voltage profiles, reducing the impact of complementary bit interdependency while maintaining high storage density.
3Reliability
If more erase pulses are applied to ensure complete erasure, then erasure completeness improves, but over-erasing occurs and device reliability decreases
Solution Approach 1:
The patent implements feedback by incorporating verification steps between erase pulses. The memory cells are periodically checked to determine if erasure is complete, and the ramped voltage process is adjusted or terminated based on this feedback, preventing over-erasing while ensuring complete erasure when needed.
Solution Approach 2:
The dynamic ramped voltage approach allows the erase process to adapt to the actual erasure progress of each memory cell, applying just the right amount of voltage to achieve complete erasure without excessive voltage application that would cause over-erasing and reliability degradation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The ramped voltage gate erasure technique significantly reduces the number of pulses required to erase memory cells, enhances reliability, and decreases power usage, maintaining efficiency even after device cycling, compared to conventional fixed voltage techniques.
Implementation Method 1
In order to erase a typical single bit, stacked gate, flash memory cell, a relatively high voltage is applied to the source (e.g., +5 volts), and the control gate is held at a high negative potential (e.g., −10 volts), while the drain is allowed to float. Under these conditions, a strong electric field is developed across the tunnel oxide between the floating gate and the source. The electrons that are trapped in the floating gate flow are forced into the source region by way of Fowler-Nordheim tunneling through the tunnel oxide.
Data Source
AI summary
A method of erasing a block of flash memory cells by applying a ramped gate erase voltage to the block of memory cells. When an erase verify of the block of memory cells indicates that erasure has not been successfully completed another erase voltage with a greater absolute value than the initial erase voltage can be applied to the block of memory cells until erasure is complete.