Ramped Interconnect Structure for Gap-Free Semiconductor Layer Connections
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Solution Overview
Problem
Existing semiconductor fabrication techniques face challenges with vertical interconnect access (VIA) such as non-conductive gaps, rough conductive material insertion, and mechanical instability due to the vertical filling of conductive material, which impede conductivity between circuit layers.
Innovation Solution
The use of additive manufacturing techniques, specifically 3D printing with conductive inks, to create a ramped interconnect access (RIA) between layers, allowing for a non-vertical conductive path that addresses the issues of vertical hole filling and mechanical support by forming a ramped structure with controlled ink deposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If vertical hole filling is used to create VIA, then electrical connection between layers is achieved, but non-conductive gaps occur at the lower portion of the VIA
Solution Approach 1:
The patent transitions from vertical hole filling (1D vertical path) to a ramped structure (2D inclined path). The conductive material is deposited along a ramped surface rather than being filled vertically, allowing controlled deposition from top to bottom without forming gaps at the lower portion.
Solution Approach 2:
The ramped structure is formed before conductive material deposition. The ramp surface is prepared in advance with specific roughness characteristics that control how the conductive material adheres and flows during deposition, preventing gap formation before the filling process begins.
2Reliability
If vertical hole filling is used to create VIA, then electrical connection is established, but conductive material gets caught along the VIA side walls
Solution Approach 1:
The patent changes from vertical insertion to ramped surface deposition. The conductive material is deposited along an inclined ramp surface rather than being inserted vertically into a hole, eliminating the side wall adhesion problem that occurs with vertical filling.
Solution Approach 2:
The ramped surface has specific local roughness characteristics that are optimized for conductive material deposition. The surface roughness is controlled to allow smooth material flow and adhesion without creating points where material gets trapped, addressing the local quality of the deposition surface.
3Reliability
If vertical hole filling is used to create VIA, then electrical connection is achieved, but open holes are created in the VIA that adversely affect conductivity
Solution Approach 1:
The patent replaces vertical hole filling with ramped surface deposition. The conductive material is laid down along a ramped path rather than being filled into a vertical hole, preventing the formation of open holes and maintaining continuous conductive pathways.
Solution Approach 2:
The ramped structure is prepared in advance to prevent open hole formation. By controlling the surface geometry and roughness before deposition, the patent ensures that conductive material deposits continuously without forming voids or open holes that would compromise integrity.
4Reliability
If vertical hole filling is used to create VIA, then electrical connection is established, but mechanical instability occurs due to lack of support
Solution Approach 1:
The patent changes from vertical suspension to ramped surface support. The conductive material is deposited on a ramped surface that provides continuous mechanical support from the substrate upward, rather than relying on vertical adhesion alone to support the weight of the conductive material.
Solution Approach 2:
The ramped structure with controlled roughness is formed in advance to provide mechanical support. The surface geometry is prepared beforehand to ensure proper adhesion and mechanical stability of the conductive material as it is deposited, preventing instability before it occurs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances conductivity and stability by providing a reliable electrical connection between layers, avoiding non-conductive gaps and mechanical instability, while allowing for refined control of ink placement and thickness, thus improving the overall performance of interlayer connections.
Implementation Method 1
an additively manufactured conductive trace formed on the ramp to electrically connect the at least one first electrical component and the at least one second electrical component
Data Source
AI summary
The disclosure is and includes at least an apparatus, system and method for a ramped electrical interconnection for use in semiconductor fabrications. The apparatus, system and method includes at least a first semiconductor substrate having thereon a first electrical circuit comprising first electrical components; a second semiconductor substrate at least partially covering the first electrical circuit, and having thereon a second electrical circuit comprising second electrical components; a ramp formed through the second semiconductor substrate between at least one of the first electrical components and at least one of the second electrical components; and an additively manufactured conductive trace formed on the ramp to electrically connect the at least one first electrical component and the at least one second electrical component.