Ramped Semiconductor Interconnects to Eliminate VIA Fill Gaps

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Solution Overview

Problem

Existing semiconductor fabrication techniques using vertical interconnect access (VIA) face challenges such as non-conductive gaps, rough VIA walls, open holes, and mechanical instability due to difficulties in filling and coating conductive material in the vertical holes.

Innovation Solution

The implementation of a ramped interconnect, referred to as a ramp interconnect access (RIA), which uses additive manufacturing techniques to create a conductive trace on a ramp formed between two semiconductor substrates, thereby providing a non-vertical electrical connection between circuit layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If vertical interconnect access (VIA) is used to provide electrical contact between multiple layers, then electrical connection between circuit layers is achieved, but non-conductive gaps may occur at the lower portion of the VIA due to premature curing of conductive material

Engineering Contradiction:

Improveelectrical connection reliabilityVSAvoidconductive material placement precision

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The patent transitions from a vertical VIA approach to a ramped interconnect geometry that introduces an angular dimension. The conductive material is deposited along a ramped path at an angle rather than vertically, allowing the material to reach the lower circuit layer before curing completes, eliminating non-conductive gaps while maintaining connection reliability.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The conductive material is deposited along the ramped interconnect path before the curing process completes the connection. The ramped geometry allows the material to advance further along the connection path during the deposition phase, ensuring the lower portion is filled with conductive material before curing sets the structure, preventing premature gap formation.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If the VIA hole is completely filled with conductive material, then electrical conductivity is achieved, but the VIA walls become overly rough causing conductive material to get caught along the sidewalls

Engineering Contradiction:

Improveelectrical conductivityVSAvoidVIA wall smoothness

Core Design Contradiction:

ReliabilityVSShape

Solution Approach 1:

The patent employs an asymmetric ramped geometry with controlled surface characteristics. The ramped interconnect has a specific angular profile and surface roughness distribution that differs from the symmetric vertical VIA. This asymmetric design allows conductive material to flow smoothly along the ramped path without catching on overly rough sidewalls, while still achieving complete electrical conductivity.

Inventive Principle:

Principle #4Asymmetry

3Reliability

If conductive material is inserted into the vertical VIA hole, then electrical connection is established, but mechanical instability occurs due to lack of support for the vertical rise

Engineering Contradiction:

Improveelectrical connectionVSAvoidmechanical stability

Core Design Contradiction:

ReliabilityVSStability of the object's composition

Solution Approach 1:

The patent replaces the vertical cylindrical VIA geometry with a ramped interconnect featuring curved or angled surfaces. The ramped path with controlled curvature provides mechanical support along the connection trajectory, distributing stress and preventing the mechanical instability that occurs in vertical rises. The curved ramped geometry inherently provides structural support for the conductive material throughout the connection path.

Inventive Principle:

Principle #14Spheroidality (Curvature)

4Ease of manufacture

If the conductive material is roughed during insertion, then the VIA is created, but open holes are created in the VIA that adversely affect conductivity

Engineering Contradiction:

ImproveVIA creation processVSAvoidelectrical conductivity

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent changes the geometric parameters of the interconnect from vertical to ramped, and modifies the surface roughness parameters along the ramped path. The controlled surface characteristics of the ramped interconnect, with optimized roughness distribution, allow the conductive material to be deposited smoothly without creating open holes, maintaining electrical conductivity while enabling the manufacturing process.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS12211713B2Apparatus, system, and method of providing a ramped interconnect for semiconductor fabrication

Publication Date: 2025.01.28 JABIL INC

AI summary

The disclosure is and includes at least an apparatus, system and method for a ramped electrical interconnection for use in semiconductor fabrications. The apparatus, system and method includes at least a first semiconductor substrate having thereon a first electrical circuit comprising first electrical components; a second semiconductor substrate at least partially covering the first electrical circuit, and having thereon a second electrical circuit comprising second electrical components; a ramp formed through the second semiconductor substrate between at least one of the first electrical components and at least one of the second electrical components; and an additively manufactured conductive trace formed on the ramp to electrically connect the at least one first electrical component and the at least one second electrical component.