Random Address Generation Circuit for Semiconductor Memory

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Solution Overview

Problem

The increasing integration and reduced chip size of semiconductor memory devices lead to interference between adjacent memory cells, complicating data randomization operations and increasing the area occupied by initial value generation and linear feedback shift registers, which burdens circuit layout design.

Innovation Solution

An integrated circuit that generates a first random address for data randomization and converts it into a second random address using an address conversion unit, allowing for synchronized output with a clock signal to perform mixing operations, thereby reducing the circuit area and enhancing operation speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the number of address bits is increased to increase capacity, then the capacity of the semiconductor memory device is improved, but the area of the initial value generation section and linear feedback shift register is increased

Engineering Contradiction:

ImprovecapacityVSAvoidarea of initial value generation section and linear feedback shift register

Core Design Contradiction:

Quantity of substanceVSArea of stationary object

Solution Approach 1:

The patent divides the random address generation function into two separate units: a first random address generation unit that generates a first random address, and a second random address generation unit that generates a second random address. This segmentation allows each unit to be simpler and smaller in area, while collectively providing the necessary capacity through the combination of two address generation processes

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a mixing unit as an intermediary component that combines the first random address and the second random address to generate a final random address. This mixing unit acts as a mediator that integrates the outputs of the two address generation units, enabling the system to achieve higher capacity without requiring a single large complex generator

Inventive Principle:

Principle #24Intermediary (Mediator)

2Adaptability or versatility

If the area of the initial value generation section and linear feedback shift register is increased, then the random address generation capability is improved, but the circuit layout design becomes more complex

Engineering Contradiction:

Improverandom address generation capabilityVSAvoidcircuit layout design complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent segments the random address generation capability into two independent units, each with its own initial value generation section and linear feedback shift register. This segmentation reduces the complexity of each individual unit's circuit layout while maintaining the overall random address generation capability through the coordinated operation of the two units

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The mixing unit serves as an intermediary that simplifies the overall circuit layout by providing a clear interface between the two address generation units and the rest of the system. It consolidates the complexity management by providing a structured way to combine the outputs of the two units without requiring complex integration logic

Inventive Principle:

Principle #24Intermediary (Mediator)

3Reliability

If data randomization is performed to minimize interference between adjacent memory cells, then the reliability is improved, but the operation speed is reduced

Engineering Contradiction:

Improveminimization of interference between adjacent memory cellsVSAvoidoperation speed

Core Design Contradiction:

ReliabilityVSSpeed

Solution Approach 1:

The patent segments the data randomization process into two parallel address generation operations that occur simultaneously. The first random address generation unit and the second random address generation unit operate in parallel, allowing the system to maintain high operation speed while still achieving effective data randomization through the combination of both addresses

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent ensures continuous random address generation by having both address generation units operate continuously and simultaneously. The mixing unit continuously combines the outputs of both units, ensuring that data randomization is performed without interruption or delay, thereby maintaining high operation speed while ensuring reliability

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS8769240B2Integrated circuit and semiconductor memory device using the same

Publication Date: 2014.07.01 SK HYNIX INC

AI summary

An integrated circuit includes a random address generation unit configured to generate a first random address for a data randomizing operation, an address conversion unit configured to convert the first random address and generate a second random address, and a synchronization output unit configured to sequentially output the first and second random addresses in synchronization with a clock signal.