Random Address Mapping in Non-Volatile Memory Using Interleaving
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Solution Overview
Problem
Current methods for wear leveling in non-volatile memories, such as flash memory devices, require large indirection tables to map frequently accessed logical addresses to physical pages, leading to significant overhead and impractical memory usage, especially in large storage devices like 2 terabyte SSDs.
Innovation Solution
The method involves generating a random address mapping using local and global interleaving, where a number of bits in the physical address space are selected for global and local interleaving, with a processor mapping these bits using specific functions to create a combined mapping, reducing the need for large tables and improving wear leveling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If table-based indirection methods are used to map logical addresses to physical pages for wear leveling, then uniform usage of all physical pages is achieved, but memory overhead becomes prohibitively large
Solution Approach 1:
The patent segments the address mapping function into two independent components: a global interleaving function that processes high-order address bits and a local interleaving function that processes low-order address bits. This segmentation eliminates the need for large indirection tables by replacing them with compact mathematical functions that together achieve the same wear-leveling effect.
Solution Approach 2:
The patent changes the approach from using a large static table to using two smaller functions with adjustable parameters (G bits for global interleaving and N-G bits for local interleaving). By changing the parameter G, the system can optimize between different levels of global versus local interleaving without requiring table lookups, thus reducing memory overhead while maintaining wear leveling effectiveness.
2Reliability
If a large indirection table is maintained for address mapping, then comprehensive wear leveling coverage is achieved, but device complexity increases
Solution Approach 1:
The patent extracts the address mapping functionality from a large, complex indirection table and implements it through two simpler mathematical functions. The global interleaving function handles the high-order bits and the local interleaving function handles the low-order bits, together providing comprehensive wear leveling coverage without requiring a large table structure.
Solution Approach 2:
Instead of using a physical large table that consumes memory, the patent uses mathematical functions that compute the mapping on-the-fly. The global and local interleaving functions together replicate the wear-leveling coverage that would otherwise require a large indirection table, but with minimal memory footprint and no table management overhead.
3Reliability
If frequent table updates are performed to maintain accurate address mappings, then optimal wear leveling is maintained, but processing time increases
Solution Approach 1:
The global and local interleaving functions are deterministic and self-contained, automatically providing optimal wear leveling without requiring external updates or management. The functions inherently distribute writes across all physical pages uniformly through their mathematical properties, eliminating the need for periodic table updates and associated processing time.
Solution Approach 2:
The address mapping is predetermined by the mathematical structure of the global and local interleaving functions. The wear leveling behavior is built into the function definitions themselves, so no runtime updates or adjustments are needed. The system is configured once with the function parameters and then operates autonomously to maintain optimal wear leveling.
Data Source
AI summary
Systems and methods for generating random address mapping in non-volatile memories using local and global interleaving are provided. One such method for generating a random address mapping for a non-volatile memory (NVM) involves identifying a number of bits (N) in a physical address space of the NVM, selecting G bit(s) of the N bits to be used for global interleaving, where G is less than N, determining a number of bits (N−G) to be used for local interleaving, mapping the G bit(s) using a mapping function for global interleaving, interleaving (N−G) bits using an interleaving function for local interleaving, and generating a combined mapping comprising the mapped G bit(s) and the interleaved (N−G) bits.