Random-Addressed Scan Circuit for Display Line Defect Suppression
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Solution Overview
Problem
Related display panels using metal oxide scan circuits face issues with scanning line image defects, necessitating complex circuit structures for sensing periods to suppress these defects.
Innovation Solution
A scan circuit incorporating a random addressing circuit and multiple scan units, where each unit group receives different combinations of clock signals, allowing for random addressing of subpixel rows, thereby simplifying the circuit structure while maintaining effective defect suppression.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complex circuit structures are used for sensing periods, then scanning line image defects are suppressed, but device complexity increases
Solution Approach 1:
The scan circuit is divided into multiple scan unit groups, where each group contains multiple scan units. This segmentation allows the circuit to process different row ranges independently, enabling defect suppression through selective scanning without requiring complex sensing circuits across the entire display panel.
Solution Approach 2:
The patent implements dynamic scan unit group selection through a random addressing circuit that can dynamically choose which scan unit group to activate based on received control signals. This dynamic selection mechanism enables flexible defect suppression by adapting the scanning pattern to specific defect locations without requiring fixed complex sensing circuitry.
2Device complexity
If random addressing circuit is implemented, then circuit structure is simplified, but control signal processing complexity increases
Solution Approach 1:
The random addressing circuit receives control signals in a compressed binary format (k control signals representing 2^k possible combinations) and expands them into specific scan unit group selections. This dimensional transformation from compressed control code to expanded physical addressing simplifies the overall circuit structure while the systematic decoding process manages the control signal processing complexity.
Solution Approach 2:
The random addressing circuit acts as an intermediary between the control signal input and the scan unit groups. It decodes the control signals and activates the appropriate scan unit group, thereby simplifying the direct connection complexity while systematically processing control signals through a dedicated decoding stage.
3Reliability
If multiple scan unit groups are used, then defect suppression capability is improved, but manufacturing complexity increases
Solution Approach 1:
The display panel's scan circuit is segmented into multiple scan unit groups, where each group can be independently manufactured and tested. This segmentation allows for modular manufacturing processes, reducing overall manufacturing complexity while improving defect suppression capability through selective scanning of different row ranges.
Solution Approach 2:
The patent changes the operational parameters of the scan circuit by implementing multiple scan unit groups with different row scanning ranges. This parameter differentiation allows the same basic circuit structure to be reused across multiple groups, simplifying manufacturing while enhancing defect suppression through parameter-based selection of appropriate scan groups.
Data Source
AI summary
A scan circuit is provided. The scan circuit includes a random addressing circuit and a plurality of scan units. The random addressing circuit is configured to receive 2k number of control signals, and is configured to select at least one scan unit for outputting signals based on the 2k number of control signals. The plurality of scan units includes a plurality of scan unit groups. A respective scan unit group of the plurality of scan unit groups includes m number of scan units, and is configured to receive n number of clock signals. A respective scan unit of the m number of scan units in the respective scan unit group is configured to receive n′ number of clock signals, n′<n, n′ and n being positive integers. At least two scan units of the m number of scan units are configured to receive different combinations of clock signals.