Random Bit Cell Using Nonvolatile Memory for Stable PUF Generation
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Solution Overview
Problem
Existing random bit cells using SRAM for physical unclonable functions are volatile, making them unstable due to ambient noise and requiring frequent regeneration, which compromises security systems.
Innovation Solution
A random bit cell design incorporating a latch and a nonvolatile memory cell with a floating gate transistor, allowing for unpredictable initial charge states to be stored and retrieved using Fowler-Nordheim tunneling for programming and erasing, ensuring stability and security.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SRAM is used to implement the physical unclonable function circuit, then random bits can be generated based on unpredictable physical characteristics, but the random bits are volatile and must be regenerated every time power is reset, causing instability
Solution Approach 1:
The circuit is divided into two functional segments: an SRAM latch for generating random bits based on unpredictable physical characteristics, and a nonvolatile memory cell for storing the generated bits. This segmentation allows each component to perform its specialized function - the SRAM provides unpredictability while the nonvolatile memory provides persistence across power cycles.
Solution Approach 2:
The patent introduces control elements (transistors) as intermediaries between the SRAM latch and the nonvolatile memory cell. These control elements manage the transfer of random bit values from the volatile SRAM to the nonvolatile storage, enabling the system to capture the unpredictable state before it is lost when power is reset.
2Reliability
If SRAM latch is used for random bit generation, then unpredictable initial charge status provides randomness, but ambient noise and surrounding environment significantly affect the initial charge state, changing the value of random bits
Solution Approach 1:
The system performs preliminary action by quickly capturing the random bit value from the SRAM latch into the nonvolatile memory cell immediately after generation. This preliminary capture occurs before ambient noise can significantly alter the SRAM's initial charge state, ensuring that the random value is preserved in its original form across power cycles.
3Device complexity
If volatile memory is used for random bit storage, then the circuit structure can be simple, but the random bits must be regenerated frequently, increasing power consumption
Solution Approach 1:
The patent merges two memory technologies - volatile SRAM and nonvolatile memory - into a single hybrid circuit structure. This combination allows the system to maintain the simple regenerative capability of SRAM while adding the power-saving persistence of nonvolatile memory, reducing the frequency of regeneration operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides stable, nonvolatile random bits that can be reliably stored and regenerated with low power consumption, enhancing the security and reliability of electronic devices by utilizing nonvolatile memory cells for unpredictable bit generation.
Implementation Method 1
A random bit cell design incorporating a latch and a nonvolatile memory cell with a floating gate transistor, allowing for unpredictable initial charge states to be stored and retrieved using Fowler-Nordheim tunneling for programming and erasing
Data Source
AI summary
A random bit cell includes a latch and a nonvolatile memory cell. The nonvolatile memory cell includes a storage circuit, a control element, an erase element, and a read circuit. The storage circuit is coupled to a first terminal of the latch. The storage circuit includes a floating gate transistor having a first terminal, a second terminal, and a floating gate. The control element has a first terminal coupled to a control line, and a control terminal coupled to the floating gate of the floating gate transistor. The erase element has a first terminal coupled to an erase line, and a control terminal coupled to the floating gate of the floating gate transistor. The read circuit is coupled to a bit line, a select gate line, and the floating gate of the floating gate transistor.